Patents by Inventor Ji Hwang Kim
Ji Hwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11987739Abstract: A core-shell quantum dot including a core including a first semiconductor nanocrystal, the first semiconductor nanocrystal including zinc, tellurium, and selenium and a semiconductor nanocrystal shell disposed on the core, the semiconductor nanocrystal shell including zinc and selenium, sulfur, or a combination thereof and a production thereof are disclosed, wherein the core-shell quantum dot does not include cadmium, lead, mercury, or a combination thereof, wherein the core-shell quantum dot(s) includes chlorine, wherein in the core-shell quantum dot, a mole ratio of chlorine with respect to tellurium is greater than or equal to about 0.01:1 and wherein a quantum efficiency of the core-shell quantum dot is greater than or equal to about 10%.Type: GrantFiled: May 16, 2023Date of Patent: May 21, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon-Yeong Kim, Soo Kyung Kwon, Yong Wook Kim, Ji-Yeong Kim, Jihyun Min, Sungwoo Hwang, Eun Joo Jang
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Publication number: 20240105963Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.Type: ApplicationFiled: March 6, 2023Publication date: March 28, 2024Inventors: Seung Tak Noh, Ji Han Lee, In Seok Lee, Jae Man Park, Won Jong Choi, Choong Hee Kim, Seong Hwang Kim, Jong Hoon Lee, Soo Jin Park, Seul Yi Lee
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Patent number: 11908806Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.Type: GrantFiled: October 14, 2021Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Ho Kim, Ji Hwang Kim, Hwan Pil Park, Jong Bo Shim
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Patent number: 11876083Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.Type: GrantFiled: August 20, 2021Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Dongho Kim, Ji Hwang Kim, Hwan Pil Park, Jongbo Shim
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Publication number: 20230260891Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: ApplicationFiled: April 27, 2023Publication date: August 17, 2023Inventors: JI HWANG KIM, HYUNKYU KIM, JONGBO SHIM, EUNHEE JUNG, KYOUNGSEL CHOI
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Patent number: 11728230Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.Type: GrantFiled: June 17, 2021Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Dongho Kim, Jin-Woo Park, Jongbo Shim
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Publication number: 20230238417Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Ji-hwang KIM, Jong-bo SHIM, Sang-uk HAN, Cha-jea JO, Won-il LEE
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Publication number: 20230207416Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: ApplicationFiled: March 3, 2023Publication date: June 29, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hwang KIM, Jong Bo Shim, Jang Woo Lee, Yung Cheol Kong, Young Hoon Hyun
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Patent number: 11658107Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: GrantFiled: June 21, 2022Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
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Patent number: 11637140Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: GrantFiled: March 16, 2021Date of Patent: April 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Won-il Lee
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Publication number: 20230111343Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.Type: ApplicationFiled: October 7, 2022Publication date: April 13, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Choong Bin YIM, Ji Hwang KIM, Jin-woo PARK, Jong Bo SHIM
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Publication number: 20230076184Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.Type: ApplicationFiled: July 28, 2022Publication date: March 9, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Bo SHIM, Sung Bum KIM, Ji Hwang KIM
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Patent number: 11600545Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: GrantFiled: July 15, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwang Kim, Jong Bo Shim, Jang Woo Lee, Yung Cheol Kong, Young Hoon Hyun
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Patent number: 11569201Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.Type: GrantFiled: October 25, 2021Date of Patent: January 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoeun Kim, Ji Hwang Kim, Jisun Yang, Seunghoon Yeon, Chajea Jo, Sang-Uk Han
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Publication number: 20220319973Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Inventors: JI HWANG KIM, HYUNKYU KIM, JONGBO SHIM, EUNHEE JUNG, KYOUNGSEI CHOI
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Patent number: 11367679Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: GrantFiled: September 10, 2020Date of Patent: June 21, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
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Patent number: 11367714Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.Type: GrantFiled: April 10, 2020Date of Patent: June 21, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jangwoo Lee, Jongbo Shim, Ji Hwang Kim, Yungcheol Kong, Youngbae Kim, Taehwan Kim, Hyunglak Ma
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Publication number: 20220173082Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.Type: ApplicationFiled: August 20, 2021Publication date: June 2, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Dongho KIM, Ji Hwang KIM, Hwan Pil PARK, Jongbo SHIM
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Publication number: 20220165680Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.Type: ApplicationFiled: October 14, 2021Publication date: May 26, 2022Inventors: DONG HO KIM, JI HWANG KIM, HWAN PIL PARK, JONG BO SHIM
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Publication number: 20220115281Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate. wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.Type: ApplicationFiled: June 17, 2021Publication date: April 14, 2022Inventors: JI HWANG KIM, DONGHO KIM, JIN-WOO PARK, JONGBO SHIM