Abstract: A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

Abstract: The present invention discloses a memory read/write arbitrating apparatus and method, which arbitrates a plurality of reading and writing requests from the CPU. The arbitrating apparatus includes a writing queue and a reading queue, a comparator, and an arbitrator. Before one writing request sending from CPU stored to the writing queue, the comparator compares the current writing request address with a previous one writing request address. Then, the comparison result and the writing request are stored in the writing queue. If the comparison result shows that the current writing request address belongs to the different memory page but to the same memory sub-bank with the previously executed writing request address and at least one reading request is present in the reading queue, the reading request will be executed preferentially.

Abstract: A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

Abstract: In DRAM system where quad rate transmission is used, at least one latch is disposed within a switching circuit for increasing the data valid windows of a portion of transmitted data segments. For example, in a sequence of transmitted data segments, only the odd numbered segments are having their data valid windows increased. Thereby, the writing process of the system is improved. The system further provides at least one delay circuit for suitably matching signals for a desired result.

Abstract: A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.

Abstract: A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

Abstract: Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.

Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

Abstract: A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

Abstract: A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit.

Abstract: A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.

Abstract: A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

Abstract: A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

Abstract: A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

Abstract: A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.

Abstract: The invention monitors the CPU cycle accessing the local bus device and records the address in its internal buffers. For any cycle addressed within a predetermined page of that address, the invention first stores the data into post-write buffer and thereafter immediately responds with READY signal to terminate the CPU cycle. For cycle addressed out of the predetermined page, this cycle would not have benefit from the post-write buffer and this new address value is recorded as a result and a new page is redefined dynamically if the address is responded by a local-bus device. The address page is dynamically defined at all time to meet the current behavior of the program running. Though a page miss could happen, however, the performance degradation is a minimal.

Abstract: A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.

Abstract: A phase lock device and method applicable to a data transmission system, particularly to a high speed transmission system are provided. Based on that the optimum operation margin for delaying data strobe is to shift the edge of data strobe to the middle region of data signal, the phase lock device and method suggest a solution, by analyzing the influence of environmental and operational conditions on delaying data strobe and system clock, to adapt delay element to the variation of environmental and operational conditions, so that the delay of data strobe is always in such a range that the data receiver can be enabled to do accurate and reliable data reading, regardless of external interference.

Abstract: An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has enough setup time at the rising edge of work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP. Therefore, the memory can function normally even if the memory is operated at high speed or with heavy loading.

Abstract: A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of the memory circuit, and then writing the data to a memory of the memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write command to the memory for writing the data to the memory without further pre-charging and activating the designative memory page.