Patents by Inventor Jijun Sun
Jijun Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12167702Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.Type: GrantFiled: March 20, 2023Date of Patent: December 10, 2024Assignee: Everspin Technologies, Inc.Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
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Publication number: 20240397731Abstract: A magnetoresistive stack, including an electrically conductive material, and a seed region disposed above the electrically conductive material and including chromium (Cr). A chromium content of the seed region is large enough to render the seed region substantially non-magnetic. The magnetoresistive stack includes a fixed magnetic region disposed above the seed region. The fixed magnetic region includes a synthetic antiferromagnetic structure including a first ferromagnetic region disposed above the seed region, a coupling layer disposed on and in contact with the first ferromagnetic region, and a second ferromagnetic region disposed on and in contact with the coupling layer. The magnetoresistive stack includes one or more dielectric layers disposed above the second ferromagnetic region, and a free magnetic region disposed above the one or more dielectric layers.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Sanjeev AGGARWAL, Han-Jong CHIA, Jon SLAUGHTER, Renu WHIG
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Patent number: 12137616Abstract: A method of fabricating a magnetoresistive device includes forming a magnetically fixed region on one side of an intermediate region. Forming the magnetically fixed region may include forming a first ferromagnetic region and forming an antiferromagnetic coupling region on one side of the first ferromagnetic region. The method may also include treating a surface of the coupling region by exposing the surface to a gas, and forming a second ferromagnetic region on the treated surface of the coupling region.Type: GrantFiled: November 14, 2018Date of Patent: November 5, 2024Assignee: Everspin Technologies, Inc.Inventor: Jijun Sun
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Publication number: 20240341199Abstract: A method of fabricating a magnetoresistive device may comprise forming an electrically conductive region and forming a first seed region on one side of the electrically conductive region. A surface of the first seed region may be treated by exposing the surface to a gas. A second seed region may be formed on the treated surface of the first seed region. The method may also comprise forming a magnetically fixed region on one side of the second seed region.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Applicant: Everspin Technologies, Inc.Inventor: Jijun SUN
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Publication number: 20240306516Abstract: Aspects of the present disclosure are directed to magnetoresistive stacks including regions having increased height-to-diameter ratios. Exemplary magnetoresistive stacks (for example, used in a magnetic tunnel junction (MTJ) magnetoresistive device) of the present disclosure include one or more multilayer synthetic antiferromagnetic structures (SAFs) or synthetic ferromagnetic structures (SyFs) in order to promote stability of the SAF or SyF, e.g., for smaller-sized MTJs.Type: ApplicationFiled: May 15, 2024Publication date: September 12, 2024Applicant: Everspin Technologies, Inc.Inventor: Jijun SUN
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Patent number: 12089418Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).Type: GrantFiled: March 17, 2023Date of Patent: September 10, 2024Assignee: Everspin Technologies, Inc.Inventors: Jijun Sun, Sanjeev Aggarwal, Han-Jong Chia, Jon M. Slaughter, Renu Whig
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Patent number: 12052928Abstract: A magnetoresistive stack may include: a fixed region having a fixed magnetic state, a spacer region, a first dielectric layer and a second dielectric layer, where both the first dielectric layer and the second dielectric layer are between the fixed region and the spacer region, and a free region between the first dielectric layer and the second dielectric layer. The free region may be configured to have a first magnetic state and a second magnetic state. The free region may include an interface layer, a multilayer structure, an insertion layer (e.g., a metallized insertion layer), one or more ferromagnetic layers (e.g., metallized ferromagnetic layers), and/or a transition layer (e.g., a metallized transition layer).Type: GrantFiled: August 9, 2021Date of Patent: July 30, 2024Assignee: Everspin Technologies, Inc.Inventor: Jijun Sun
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Patent number: 12052927Abstract: A method of fabricating a magnetoresistive device may comprise forming an electrically conductive region and forming a first seed region on one side of the electrically conductive region. A surface of the first seed region may be treated by exposing the surface to a gas. A second seed region may be formed on the treated surface of the first seed region. The method may also comprise forming a magnetically fixed region on one side of the second seed region.Type: GrantFiled: August 22, 2019Date of Patent: July 30, 2024Assignee: EVERSPIN TECHNOLOGIES, INC.Inventor: Jijun Sun
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Patent number: 12022741Abstract: Aspects of the present disclosure are directed to magnetoresistive stacks including regions having increased height-to-diameter ratios. Exemplary magnetoresistive stacks—for example, used in a magnetic tunnel junction (MTJ) magnetoresistive device—of the present disclosure include one or more multilayer synthetic antiferromagnetic structures—SAFs—or synthetic ferromagnetic structures—SyFs—(A) in order to promote stability of the SAF or SyF, e.g., for smaller-sized MTJs (200).Type: GrantFiled: October 17, 2019Date of Patent: June 25, 2024Assignee: EVERSPIN TECHNOLOGIES, INC.Inventor: Jijun Sun
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Publication number: 20240114802Abstract: A magnetoresistive stack may include a fixed magnetic region, where the fixed magnetic region may include a reference layer, an interfacial layer disposed above the reference layer, an intermediate layer disposed above the interfacial layer, and a free magnetic region disposed above the intermediate layer. The interfacial layer may include cobalt (Co).Type: ApplicationFiled: October 2, 2023Publication date: April 4, 2024Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Kerry Joseph NAGEL
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Patent number: 11937436Abstract: A magnetoresistive stack includes a fixed magnetic region, one or more dielectric layers disposed on and in contact with the fixed magnetic region, and a free magnetic region disposed above the one or mom dielectric layers. The fixed magnetic region may include a first ferromagnetic region, a coupling layer, a second ferromagnetic region, a transition layer disposed, a reference layer, and at least one interfacial layer disposed above the second ferromagnetic region. Another interfacial layer may be disposed between the one or more dielectric layers and the free magnetic region.Type: GrantFiled: October 29, 2019Date of Patent: March 19, 2024Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Jijun Sun, Han-Jong Chia, Sarin Deshpande, Ahmet Demiray
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Publication number: 20230380297Abstract: A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Jon SLAUGHTER, Renu WHIG
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Publication number: 20230309416Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.Type: ApplicationFiled: March 20, 2023Publication date: September 28, 2023Applicant: Everspin Technologies, Inc.Inventors: Sumio IKEGAWA, Han Kyu Lee, Sanjeev AGGARWAL, Jijun SUN, Syed M. ALAM, Tom ANDRE
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Patent number: 11758823Abstract: A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.Type: GrantFiled: November 13, 2018Date of Patent: September 12, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Jijun Sun, Jon Slaughter, Renu Whig
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Publication number: 20230263071Abstract: A magnetoresistive stack may include a first electrically conductive material, a fixed region having a fixed magnetic state, a free region configured to have a first magnetic state and a second magnetic state, a dielectric layer disposed between the fixed region and the free region, a spacer region, and a cap layer disposed between the spacer region and the free region. The free region may include a layer of ferromagnetic material, an insertion layer, an iPMA layer, and/or a low saturation magnetization layer.Type: ApplicationFiled: February 11, 2022Publication date: August 17, 2023Applicant: Everspin Technologies, Inc.Inventors: Sumio IKEGAWA, Jijun SUN, Monika ARORA
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Publication number: 20230225135Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).Type: ApplicationFiled: March 17, 2023Publication date: July 13, 2023Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Sanjeev AGGARWAL, Han-Jong CHIA, Jon M. SLAUGHTER, Renu WHIG
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Patent number: 11690229Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).Type: GrantFiled: December 23, 2020Date of Patent: June 27, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Jijun Sun, Sanjeev Aggarwal, Han-Jong Chia, Jon M. Slaughter, Renu Whig
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Patent number: 11637235Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.Type: GrantFiled: January 16, 2020Date of Patent: April 25, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
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Publication number: 20230047005Abstract: A magnetoresistive stack may include: a fixed region having a fixed magnetic state, a spacer region, a first dielectric layer and a second dielectric layer, where both the first dielectric layer and the second dielectric layer are between the fixed region and the spacer region, and a free region between the first dielectric layer and the second dielectric layer. The free region may be configured to have a first magnetic state and a second magnetic state. The free region may include an interface layer, a multilayer structure, an insertion layer (e.g., a metallized insertion layer), one or more ferromagnetic layers (e.g., metallized ferromagnetic layers), and/or a transition layer (e.g., a metallized transition layer).Type: ApplicationFiled: August 9, 2021Publication date: February 16, 2023Applicant: Everspin Technologies, Inc.Inventor: Jijun SUN
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Patent number: 11488647Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.Type: GrantFiled: June 27, 2019Date of Patent: November 1, 2022Assignee: Everspin Technologies, Inc.Inventors: Jijun Sun, Frederick Mancoff, Jason Janesky, Kevin Conley, Lu Hui, Sumio Ikegawa