Abstract: Data destined for memory, i.e., data that was evicted at some level in the cache hierarchy is intercepted and subjected to compression before being sent to memory. Thereby, when the compression is successful, the memory bandwidth requirement is reduced, potentially resulting in higher performance and/or energy efficiency in some embodiments.

Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.

Abstract: A PCS culling technique may be augmented utilizing a motion blur (three-dimensional) rasterizer. The culling technique can be used for continuous collision detection.

Abstract: In one embodiment the table pointed to by visibility samples in Degradation Coverage-Based Anti-Aliasing is split up so that more values can fit (but each value uses fewer bits). This way, more values can be represented in a pixel, and this leads to better image quality in some embodiments. This also opens up the possibility of using as few as two values per pixel, whereas the CSAA uses four or more. Hence, this also saves bandwidth and therefore, also reduces power consumption in some embodiments.

Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.

Abstract: In accordance with some embodiments, caching may be improved for tiles on shared edges between triangles. In some embodiments, the technique may be used for either color and depth caches or both caches.

Abstract: When a tile is evicted from the cache, an attempt is made to compress the tile using any compression algorithm. The difference is that the colors of the tile are compressed as they are, but the colors can also be transformed with a color transform (for example, lossless YCoCg), and after that those colors are compressed with the same compression algorithm. Several different color transforms may be tried, and selection of which one to use can be done in several ways.

Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.

Abstract: A standard occlusion query (OQ) may be generalized to five dimensions, which can be used for motion blurred, defocused, occlusion culling. As such, the occlusion query concept is generalized so that it can be used within 5D rasterization, which is used for rendering of motion blur and depth of field. For 5D rasterization, occlusion culling may be done with OQs as well, applied to solve other rendering related problems.

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described.

Abstract: In accordance with some embodiments, caching may be improved for tiles on shared edges between triangles. In some embodiments, the technique may be used for either color and depth caches or both caches.

Abstract: In accordance with some embodiments, a mask or table may be maintained to record information about whether or not each pixel within a tile is cleared. As used herein, a “cleared” tile is one that is not covered by any other depicted objects. The clear mask may store a bit per pixel or sample to indicate whether the pixel or sample contains a color value or whether it is cleared. As a result, the compression ratio may be increased for partially covered tiles in some embodiments.

Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.

Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.

Abstract: A color buffer cache may be implemented in a way that reduces memory bandwidth. In one embodiment this may be done by determining whether a corresponding tile being rendered is completely inside a triangle. If so, the cache lines that correspond to this tile may be marked as “less useful”. As a result of being marked as less useful, those cache lines may be replaced before other cache lines in one embodiment. Thus a color buffer cache is used for those tiles that overlap with at least one triangle edge. The use of such a color buffer cache scheme may be more efficient and therefore may reduce memory bandwidth in some embodiments.

Abstract: In accordance with some embodiments, depth values may be split into more and less significant bits. By so doing, some processing can be done based only on the more significant bits. Where the number of more significant bits is significantly less than the total number of bits, some memory bandwidth can be preserved. In other words, by only using the more significant bits for some of the depth buffering operations, memory bandwidth usage can be reduced, improving efficiency.

Abstract: A per-tile test in the 5D rasterizer outputs intervals for both lens parameters, (u,v), and for time, t, as well as for depth z. These intervals are conservative bounds for the current tile for 1) the visible lens region, 2) the time the triangle overlaps the tile, and 3) the depth range for the triangle inside the tile.

Abstract: In accordance with some embodiments, the number of bits allocated to depth compression may be changed variably based on a number of considerations. As a result, depth data may be compressed in a more efficient way.

Abstract: A depth cache keeps the depth data in compressed format when possible. This involves a more flexible cache implementation, where a tile may occupy a variable amount of cache lines depending on whether it can be compressed or not. One advantage of some embodiments this depth cache is that the effective cache size increases proportionally to the compression ratio. The memory bandwidth can be reduced, compared to a system compressing the data after the cache in some embodiments. Alternatively, pre-cache compression may increase the effective cache size by a factor of two or more, compared to a post-cache compressor, at equal or higher performance.