Patents by Inventor Jim Maveety

Jim Maveety has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9466595
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die does not comprise using an interfacial glue.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Jim Maveety
  • Patent number: 7365003
    Abstract: A method and structure for using porous diamond interlayer dielectrics (ILDs) in conjunction with carbon nanotube interconnects is herein described. A diamond ILD is deposited on an underlaying layer. The diamond layer is optionally and selectively removed of non-sp3 bond to create a porous diamond film. Trenches and vias are etched in the porous diamond ILD. Carbon nanotubes are deposited on the diamond ILD filling the trenches using a liquid crystal host-carbon nanotube solution. Using methods of nematic liquid crystal alignment, the carbon nanotubes are aligned under the influence of the liquid crystals. At least some of the liquid crystal solution is removed leaving an aligned carbon nanotubes.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Tan Shida, Jim Maveety
  • Publication number: 20060138658
    Abstract: A method and structure for using porous diamond interlayer dielectrics (ILDs) in conjunction with carbon nanotube interconnects is herein described. A diamond ILD is deposited on an underlaying layer. The diamond layer is optionally and selectively removed of non-sp3 bond to create a porous diamond film. Trenches and vias are etched in the porous diamond ILD. Carbon nanotubes are deposited on the diamond ILD filling the trenches using a liquid crystal host-carbon nanotube solution. Using methods of nematic liquid crystal alignment, the carbon nanotubes are aligned under the influence of the liquid crystals. At least some of the liquid crystal solution is removed leaving an aligned carbon nanotubes.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 29, 2006
    Inventors: Kramadhati Ravi, Tan Shida, Jim Maveety
  • Publication number: 20060128061
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die does not comprise using an interfacial glue.
    Type: Application
    Filed: February 3, 2006
    Publication date: June 15, 2006
    Inventors: Kramadhati Ravi, Jim Maveety
  • Publication number: 20060073636
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die does not comprise using an interfacial glue.
    Type: Application
    Filed: October 4, 2004
    Publication date: April 6, 2006
    Inventors: Kramadhati Ravi, Jim Maveety
  • Patent number: 6794223
    Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jim Maveety, Quan Tran
  • Publication number: 20040087061
    Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.
    Type: Application
    Filed: June 23, 2003
    Publication date: May 6, 2004
    Inventors: Qing Ma, Jim Maveety, Quan Tran
  • Patent number: 6617682
    Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jim Maveety, Quan Tran
  • Patent number: 6443749
    Abstract: An electrical socket connection for coupling a conductive pin to a circuit board. The socket has several contact points that can be expanded to create an opening sufficiently sized to allow the conductive pin to pass through the contact points with minimal insertion force. After the pin is inserted, the contact points can be retracted to form electrical interconnects with the pin. The contacts are electrically coupled to the remaining circuitry via the socket. The present invention, therefore, provides a zero insertion force socket that has multiple contact points and does not require secondary movement of the pin or circuit package.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: September 3, 2002
    Assignee: Intel Corporation
    Inventors: Michael P. Brownell, Jim Maveety
  • Publication number: 20020013100
    Abstract: An electrical socket connection for coupling a conductive pin to a circuit board. The socket has several contact points that can be expanded to create an opening sufficiently sized to allow the conductive pin to pass through the contact points with minimal insertion force. After the pin is inserted, the contact points can be retracted to form electrical interconnects with the pin. The contacts are electrically coupled to the remaining circuitry via the socket. The present invention, therefore, provides a zero insertion force socket that has multiple contact points and does not require secondary movement of the pin or circuit package.
    Type: Application
    Filed: March 28, 2000
    Publication date: January 31, 2002
    Inventors: Michael P. Brownell, Jim Maveety