Fabrication of stacked die and structures formed thereby

Abstract

Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die does not comprise using an interfacial glue.

Description

This U.S. Patent application is a divisional of U.S. patent application Ser. No. 10/958,511 filed Oct. 4, 2004.

FIELD OF THE INVENTION

The present invention generally relates to the field of microelectronic devices, and more particularly to methods of fabricating stacked die structures without the use of an interfacial glue.

BACK GROUND OF THE INVENTION

Integrated circuits form the basis for many electronic systems. An integrated circuit may include a vast number of transistors and other circuit elements that may be formed on a single semiconductor wafer or chip and may be interconnected to implement a desired function.

Many modern electronic systems are created through the use of a variety of different integrated circuits; each integrated circuit performing one or more specific function. For example, computer systems may include at least one microprocessor and a number of memory chips. Conventionally, each of these integrated circuits are formed on a separate chip, packaged independently and interconnected on, for example, a printed circuit board (PCB).

As integrated circuit technology progresses, there is a growing desire for a “system on a chip”, in which the functionality of all of the integrated circuit devices of the system are packaged together without a conventional PCB. In practice, various “system modules” have been introduced that electrically connect and package integrated circuit devices which are fabricated on the same or on different semiconductor wafers. Initially, system modules have been created by simply stacking two chips, e.g., a logic and memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip structure. Subsequently, multi-chip module (MCM) technology has been utilized to stack a number of chips on a common substrate to reduce the overall size and weight of the package, which directly translates into reduced system size.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing out and distinctly claiming certain embodiments of the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:

FIGS. 1a-1e represent structures according to an embodiment of the present invention.

FIG. 2 represents a structure according to an embodiment of the present invention.

FIG. 3 represents a structure according to another embodiment of the present invention.

FIG. 4 represents a system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.

Methods and associated structures of forming and utilizing a microelectronic device are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, without the use of an interfacial glue. In this manner, improved thermal and electrical contact, as well as a decrease in stress between the bonded die, can be achieved.

FIGS. 1a-1e illustrate an embodiment of a method of forming stacked die structures. FIG. 1a illustrates a device wafer 100. The device wafer 100 may be comprised of materials such as, but not limited to, silicon, silicon-on-insulator, silicon on diamond, or combinations thereof. The device wafer 100 may comprise a device portion 103, and a non-device portion 104. The non-device portion 104 of the device wafer 100 may comprise a first thickness 106. The device wafer 100 may comprise a plurality of die 101, as are known in the art. The plurality of die 101 may comprise various functionalities, such as, but not limited to, a memory functionality and/or a logic functionality, as are well known in the art.

The non-device portion 104 of the device wafer 100 may be thinned utilizing a grinding and/or a polishing technique, as are known in the art (FIG. 1b). The non-device portion 104 of the device wafer 100 may be thinned to a thinned thickness 108. In one embodiment, the thinned thickness 108 may range from about 50 to about 200 microns. The device wafer 100 may then be separated into a plurality of individual die 102 utilizing methods well known to those skilled in the art, such as but not limited to wafer sawing, which serve to separate the plurality of die 101 from each other (FIG. 1c).

The plurality of individual die 102 may comprise a device side 110 and a non-device side 112. In one embodiment, the non-device side 112 may comprise silicon. The device side 110 may comprise various circuit elements, such as but not limited to transistors, resistors etc. as are well known in the art. In one embodiment, a first individual die 102a may comprise a device side 110a and a non-device side 112a (FIG. 1d). A second individual die 102b may comprise a device side 110b and a non-device side 112b. The non-device side 112a of the first individual die 102a may be brought into contact with the non-device side 112b of the second individual die 102b to form a stacked die structure 116 (FIG. 1e).

Upon contacting the non-device side 112a of the first individual die 102a with the non-device side 112b of the second individual die 102b, a bond 114 may be formed by direct silicon to silicon bonding between the non-device side 112a of the first individual die 102a and the non-device side 112b of the second individual die 102b. The bond 114 may be formed due to Van der Waal forces that may develop between the non-device side 112a (which may comprises silicon) of the first individual die 120a and the non-device side 112b (which also preferably comprises silicon) of the second individual die 102b. In one embodiment, the bond 114 can be further strengthened by heating the stacked die structure 116 to a temperature up to about 450 degrees Celsius, and in another embodiment, by heating from about 250 degrees to about 450 degrees Celsius.

Forming the bond 114 by utilizing direct silicon to silicon bonding according to the methods of the present embodiment alleviates the need for using an interfacial glue, i.e., polymers, adhesives, solders, and other such materials commonly used to join one die to another, as are well known in the art. The elimination of such an interfacial glue, or joining material, to form the bond 114 between the first individual die 102a and the second individual die 102b results in better thermal and electrical contact between the die, due to the low coefficient of thermal expansion (CTE) differences between the die. The CTE differences between the die may be approximately zero when both of the die comprise silicon, for example.

Thus, deleterious thermal barriers may be eliminated between the die joined according to the methods of the present embodiment. In addition, stress between die joined according to the present embodiment are greatly reduced, if not eliminated due to the matching of the CTE's between the joined die. Yet another advantage of joining the die without the use of interfacial glue is that the directly bonded die reinforce each other by increasing rigidity and reducing the strain that would typically be introduced by joining the die with an interfacial glue. Increasing rigidity and reducing strain decreases undesirable shifts in electrical parameters. Yet another advantage of the present embodiment is that the mechanical strength of the bond 114 is improved by utilizing direct silicon to silicon bonding, and in one embodiment the mechanical strength of the bond may comprise at least about 1500 KPa.

FIG. 2 depicts an embodiment of a stacked die structure 216 that may comprise a first individual die 202a, a second individual die 202b, a third individual die 202c, and a fourth individual die 202d. In one embodiment, the individual die 202a, 202b, 202c, 202d may comprise various functionalities, such as but not limited to memory functionalities and/or logic functionalities. The individual die 202a, 202b, 202c, 202d may comprise device sides 210a, 210b, 210c, 210d and non-device sides 212a, 212b, 212c, 212d, respectively. In one embodiment, the non-device sides 212a, 212b, 212c, 212d may preferably comprise silicon.

The non-device side 212a of the first individual die 202a may be bonded to the non-device side 212b of the second individual die 202b (by direct silicon to silicon bonding, as described above) to form a bond 214a, similar to the bond 114 in FIG. 1e. The bond 214a does not comprise an interfacial glue. In like manner, the non-device side 212c of the third individual die 202c may be bonded to the non-device side 212d of the fourth individual die 202d to form a bond 214b, that is similar to the bond 114 of FIG. 1e, and which does not comprise an interfacial glue.

The device side 210a of the first individual die 202a may comprise a first array of contacts 206a, such as but not limited to ball grid array contacts, for example. Similarly, the device side 210b of the second individual die 202b may comprise an second array of contacts 206b. The first array of contacts 206a may be electrically contacted and/or attached to a bottom surface 215a of a first land grid array 208a, as is well known in the art. The first land grid array may also comprise a top surface 213a. The second array of contacts 206b may be electrically connected and/or attached to a top surface 213b of a second land grid array 208b.

The first land grid arrays 208a and the second land grid array 208b may comprise a first organic land grid array and a second organic land grid array, but may comprise any such suitable substrate that may be electrically and/or physically connected to a semiconductor die. It will be understood by those in the art that the land grid arrays 208a, 208b may comprise an array of contacts (not shown) on both their top sides 213a, 213b, and their bottom sides 215a, 215b that correspond and are in electrical and/or physical connection with the array of contacts 206a, 206b. Thus, the non-device sides 212a, 212b of the first and the second individual die 202a, 202b may be bonded together by direct silicon to silicon bonding, and the device sides 210a, 210b of the first and second individual die 202a, 202b may be further connected to land grid array substrates 208a, 208b by an array of contacts 206a, 206b.

The third individual die 202c may be electrically connected and/or attached to a bottom surface 215b the second land grid array 208b by a third array of contacts 206c on the device side 210c of the individual die 202c. The fourth individual die 202d may be electrically connected and/or attached to a top surface 213c a third land grid array 208c by a fourth array of contacts 206d on the device side 210d of the fourth individual die 202d. The third land grid array 208c may also comprise a bottom surface 215c. It will be understood by those skilled in the art that the number of levels of die and/or land grid arrays that may be stacked will vary according to a particular design application. Thus, the current embodiment enables the formation of stacked die structures that possess a high strength, low stress bond between the stacked die, without the use of an interfacial glue.

FIGS. 3 depicts another embodiment of the present invention. FIG. 3 illustrates a cross-section of a stacked die structure 316. The stacked die structure 316 may comprise a first individual die 302a, a second individual die 302b, a third individual die 302c, and a fourth individual die 302d. The individual die 302a, 302b, 302c, 302d may comprise device sides 310a, 310b, 310c, 310d, respectively, that may preferably comprise silicon, and non-device sides 312a, 312b, 312c, 312d, respectively, that may preferably comprise a diamond material, or other equivalent films, as are well known in the art. The diamond material may be formed by any such technique known in the art used to form diamond films, such as, but not limited to, plasma enhanced chemical vapor deposition (PECVD).

A first polysilicon layer 311a, a second polysilicon layer 311b, a third polysilicon layer 311c, and a fourth polysilicon layer 311d, as are well known in the art, may be disposed between the non-device sides 312a, 312b, 312c, 312d and the device sides 310a, 310b, 310c, 310d respectively. The polysilicon layers 311a, 311b, 311c, 311d may serve as an adhesion layer between the non-device layers 312a, 312b, 312c, 312d and the device layers 310a, 310b, 310c, 310b.

The non-device side 312a of the first individual die 302a may be bonded to the non-device side 312b of the second individual die 302b (by direct silicon to silicon bonding, as described above) to form a bond 314a, similar to the bond 114 in FIG. 1e. The bond 314a does not comprise an interfacial glue. In like manner, the non-device side 312c of the third individual die 302c may be bonded to the non-device side 312d of the fourth individual die 302d to form a bond 314b, that is also similar to the bond 114 of FIG. 1e, and which does not comprise an interfacial glue.

The device sides 310a, 310b, 310c, 310d may comprise an array of contacts 306a, 306b, 306c, 306d such as but not limited to ball grid array contacts, for example. The array of contacts 306a may be electrically connected and/or attached to a bottom surface 315b of a first land grid array 308a. The first land grid array 308a may also comprise a top surface 313a. The array of contacts 306b may be electrically connected and/or attached to a top surface 313b of a second land grid array 308b. The array of contacts 306c may be electrically connected and/or attached to a bottom surface 315b of the second land grid array 308b. The array of contacts 306d may be electrically contacted and/or attached to a top surface 313c of a third land grid array 308c. The third land grid array 308c may also comprise a bottom surface 315c. The land grid arrays 308a, 308b and 308c may comprise an organic land grid array, but may comprise any such suitable substrate that may be electrically connected to a semiconductor die.

It will be understood by those skilled in the art that the number of levels of die that may be stacked will vary according to the particular design application. The current embodiment enables the formation of stacked die structures that possess a high strength, low stress bond between the stacked die, without the use of an interfacial glue. In addition, since the current embodiment preferably comprises a silicon on diamond structure, in that the non-device sides 312a, 312b, 312c, 312d preferably comprise diamond and the device sides 310a, 310b, 310c, 310d preferably comprise silicon, the stacked die structure 316 of the current embodiment greatly improves the thermal management capabilities of the stacked die structure 316 by enabling heat spreading to occur by the diamond non-device sides 312a, 312b, 312c, 312d. As detailed above, the present invention describes the formation of stacked die structures that exhibit low stress and high mechanical strength, without the use of interfacial glues between die bonded together.

FIG. 4 is a diagram illustrating an exemplary system capable of being operated with methods for fabricating stacked die structures, such as the stacked die structures 216, 316 of FIGS. 2 and 3 respectively. It will be understood that the present embodiment is but one of many possible systems in which the stacked die structures of the present invention may be used. The system 400 may be used, for example, to execute the processing by various processing tools, such as bonding tools, as are well known in the art, for the methods described herein.

In the system 400, a stacked die structure 403 may be communicatively coupled to a printed circuit board (PCB) 401 by way of an I/O bus 408. The communicative coupling of the stacked die structure 403 may be established by physical means, such as through the use of a package and/or a socket connection to mount the stacked die structure 403 to the PCB 401 (for example by the use of a chip package and/or a land grid array socket). The stacked die structure 403 may also be communicatively coupled to the PCB 401 through various wireless means (for example, without the use of a physical connection to the PCB), as are well known in the art.

The system 400 may include a computing device 402, such as a processor, and a cache memory 404 communicatively coupled to each other through a processor bus 405. The processor bus 405 and the I/O bus 408 may be bridged by a host bridge 406. Communicatively coupled to the I/O bus 408 and also to the stacked die structure 403 may be a main memory 412. Examples of the main memory 412 may include, but are not limited to, static random access memory (SRAM) and/or dynamic random access memory (DRAM), and/or some other state preserving medium. The system 400 may also include a graphics coprocessor 413, however incorporation of the graphics coprocessor 413 into the system 400 is not necessary to the operation of the system 400. Coupled to the I/O bus 408 may also, for example, be a display device 414, a mass storage device 420, and keyboard and pointing devices 422.

These elements perform their conventional functions well known in the art. In particular, mass storage 420 may be used to provide long-term storage for the executable instructions for a method for forming stacked die structures in accordance with embodiments of the present invention, whereas main memory 412 may be used to store on a shorter term basis the executable instructions of a method for forming stacked die structures in accordance with embodiments of the present invention during execution by computing device 402. In addition, the instructions may be stored, or otherwise associated with machine accessible mediums communicatively coupled with the system, such as compact disks, read only memories (CD-ROMs), digital versatile disks (DVDs), floppy disks, and carrier waves, and/or other propagated signals, for example. In one embodiment, main memory 412 may supply the computing device 402 (which may be a processor, for example) with the executable instructions for execution.

Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that various microelectronic structures, such as stacked die structures, are well known in the art. Therefore, the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.

Claims

1. A method of forming a microelectronic structure comprising;

forming a bond between a non-device side of a first individual die and a non-device side of a second individual die, wherein forming the bond between the non-device side of the first individual die and the non-device side of the second individual die does not comprise using an interfacial glue.

2. The method of claim 1 wherein forming a bond comprises forming a silicon to silicon bond comprising Van der Waal forces.

3. The method of claim 1 wherein forming a bond comprises:

bringing the non-device side of the first individual die and the non-device side of the second individual die in contact with each other; and

heating the non-device side of the first individual die and the non-device side of the second individual die to a temperature between about 250 to about 450 degrees Celsius.

4. The method of claim 1 wherein not using an interfacial glue comprises not using an interfacial glue selected from the group consisting of solder, organic adhesives and polymer adhesives.

5. The method of claim 1 wherein the non-device side of the first individual die and the non-device side of the second individual die are thinned prior to forming the bond.

6. The method of claim 5 wherein the non-device side of the first individual die and the non-device side of the second individual die are thinned to a thickness of about 50 microns to about 100 microns prior to forming the bond.

7. The method of claim 5 wherein the non-device side of the first individual die and the non-device side of the second individual die are thinned by at least one of polishing or grinding.

8. A method of forming a microelectronic structure comprising:

thinning a non-device portion of a wafer, wherein the wafer comprises a plurality of die;

separating the wafer into a plurality of individual die;

bringing the non-device side of a first individual die and the non-device side of a second individual die into contact with each other; and

forming a bond between the non-device side of the first individual die and the non-device side of the second individual die without using an interfacial glue.

9. The method of claim 8 wherein forming a bond comprises heating the non-device side of the first individual die and the non-device side of the second individual die to a temperature between about 250 to about 450 degrees Celsius.

10. The method of claim 8 wherein without using an interfacial glue comprises without using an interfacial glue selected from the group consisting of solder, organic adhesives and polymer adhesives.

11. The method of claim 8 wherein separating the wafer comprises sawing the wafer.

12. The method of claim 8 further comprising attaching a first land grid array to a device side of the first individual die and a second land grid array to a device side of the second individual die.

13. The method of claim 12 wherein attaching a first land grid array to the device side of the first individual die and a second land grid array to the device side of the second individual die comprises attaching a first organic land grid array to the device side of the first individual die and a second organic land grid array to the device side of the second individual die.