Patents by Inventor Jimin Yao

Jimin Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312803
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Jimin YAO, Shawna LIFF, Xin YAN, Numair AHMED
  • Publication number: 20200303822
    Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.
    Type: Application
    Filed: September 29, 2017
    Publication date: September 24, 2020
    Inventors: Jimin YAO, Shawna M. LIFF, William J. LAMBERT, Zhichao ZHANG, Robert L. SANKMAN, Sri Chaitra J. CHAVALI
  • Publication number: 20200243956
    Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.
    Type: Application
    Filed: January 26, 2019
    Publication date: July 30, 2020
    Applicant: INTEL CORPORATION
    Inventors: ZHENGUO JIANG, OMKAR KARHADE, SRICHAITRA CHAVALI, ZHICHAO ZHANG, JIMIN YAO, STEPHEN SMITH, XIAOQIAN LI, ROBERT L. SANKMAN
  • Patent number: 10672625
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Sergio A. Chan Arguedas, Joshua D. Heppner, Jimin Yao
  • Publication number: 20200051899
    Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Debendra MALLIK, Sanka GANESAN, Pilin LIU, Shawna LIFF, Sri Chaitra CHAVALI, Sandeep GAAN, Jimin YAO, Aastha UPPAL
  • Patent number: 10504863
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Publication number: 20190287872
    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Applicant: INTEL CORPORATION
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Richard C. Stamey, Chu Aun Lim, Jimin Yao
  • Publication number: 20190228988
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Eric Li, Shawna Liff
  • Publication number: 20190189567
    Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Kyle Yazzie, Shawna M. Liff
  • Patent number: 10297567
    Abstract: Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define a chamber. The platform can be located within the chamber and can be proximate a thermocompression chip bonder. The plasma jet can be located proximate the platform. The plasma jet can be movable about the platform. The plasma jet can include a nozzle arranged to direct a plasma gas onto the platform. Also described are other embodiments for thermocompression bonding.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Donglai David Lu, Jimin Yao, Amrita Mallik, George S. Kostiew, Shawna M. Liff
  • Patent number: 10256205
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Patent number: 10249515
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Jimin Yao, Eric Li, Shawna Liff
  • Publication number: 20190096838
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Application
    Filed: November 21, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Publication number: 20190074199
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: March 7, 2019
    Applicant: Intel Corporation
    Inventors: Sergio A. Chan Arguedas, Joshua D. Heppner, Jimin Yao
  • Publication number: 20180068969
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 8, 2018
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Patent number: 9842818
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Publication number: 20170290211
    Abstract: Templates to arrange and/or align components for batch placement on a substrate are described. A batch placement template can include a number of detents physically arranged relative to each other corresponding to a physical arrangement of components to be placed on a substrate. The detents can be sized to allow components to be manipulated into the detents and subsequently picked and placed on the substrate in a batch process.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: INTEL CORPORATION
    Inventors: DANIEL CHAVEZ-CLEMENTE, XIAO LU, JIMIN YAO
  • Publication number: 20170287735
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Eric Li, Shawna Liff
  • Publication number: 20170278816
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 28, 2017
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Patent number: 9721880
    Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Jimin Yao, Sanka Ganesan, Shawna M. Liff, Yikang Deng, Debendra Mallik