Patents by Inventor Jimin Yao
Jimin Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210098411Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
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Publication number: 20200411464Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Applicant: Intel CorporationInventors: Debendra Mallik, Sergio Antonio Chan Arguedas, Jimin Yao, Chandra Mohan Jha
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Publication number: 20200388576Abstract: Embodiments herein relate to systems, apparatuses, or processes for a layer for etched identification marks on a package. Embodiments include applying a layer to a side of a package, and laser etching the layer with an identification mark associated with the package to provide a visible identification on the package. In particular, the layer may be an EMI shielding layer of film laminate applied to the side of the package to protect the package from EMI or to protect surrounding components from EMI generated by the package. A laser or some other etching technique may then be performed on the layer to make a visible identification on the package.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Inventors: Taylor GAINES, Kosuke HIROTA, Yoshihiro TOMITA, Jimin YAO
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Publication number: 20200312803Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.Type: ApplicationFiled: March 25, 2019Publication date: October 1, 2020Inventors: Jimin YAO, Shawna LIFF, Xin YAN, Numair AHMED
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Publication number: 20200303822Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.Type: ApplicationFiled: September 29, 2017Publication date: September 24, 2020Inventors: Jimin YAO, Shawna M. LIFF, William J. LAMBERT, Zhichao ZHANG, Robert L. SANKMAN, Sri Chaitra J. CHAVALI
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Publication number: 20200243956Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.Type: ApplicationFiled: January 26, 2019Publication date: July 30, 2020Applicant: INTEL CORPORATIONInventors: ZHENGUO JIANG, OMKAR KARHADE, SRICHAITRA CHAVALI, ZHICHAO ZHANG, JIMIN YAO, STEPHEN SMITH, XIAOQIAN LI, ROBERT L. SANKMAN
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Patent number: 10672625Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.Type: GrantFiled: April 1, 2016Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Sergio A. Chan Arguedas, Joshua D. Heppner, Jimin Yao
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Publication number: 20200051899Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Debendra MALLIK, Sanka GANESAN, Pilin LIU, Shawna LIFF, Sri Chaitra CHAVALI, Sandeep GAAN, Jimin YAO, Aastha UPPAL
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Patent number: 10504863Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: GrantFiled: November 21, 2018Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Publication number: 20190287872Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.Type: ApplicationFiled: March 19, 2018Publication date: September 19, 2019Applicant: INTEL CORPORATIONInventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Richard C. Stamey, Chu Aun Lim, Jimin Yao
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Publication number: 20190228988Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.Type: ApplicationFiled: April 2, 2019Publication date: July 25, 2019Applicant: Intel CorporationInventors: Jimin Yao, Eric Li, Shawna Liff
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Publication number: 20190189567Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Applicant: Intel CorporationInventors: Jimin Yao, Kyle Yazzie, Shawna M. Liff
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Patent number: 10297567Abstract: Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define a chamber. The platform can be located within the chamber and can be proximate a thermocompression chip bonder. The plasma jet can be located proximate the platform. The plasma jet can be movable about the platform. The plasma jet can include a nozzle arranged to direct a plasma gas onto the platform. Also described are other embodiments for thermocompression bonding.Type: GrantFiled: December 18, 2015Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Donglai David Lu, Jimin Yao, Amrita Mallik, George S. Kostiew, Shawna M. Liff
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Patent number: 10256205Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: GrantFiled: November 14, 2017Date of Patent: April 9, 2019Assignee: Intel CorporationInventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Patent number: 10249515Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.Type: GrantFiled: April 1, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Jimin Yao, Eric Li, Shawna Liff
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Publication number: 20190096838Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: ApplicationFiled: November 21, 2018Publication date: March 28, 2019Applicant: Intel CorporationInventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Publication number: 20190074199Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.Type: ApplicationFiled: April 1, 2016Publication date: March 7, 2019Applicant: Intel CorporationInventors: Sergio A. Chan Arguedas, Joshua D. Heppner, Jimin Yao
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Publication number: 20180068969Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Patent number: 9842818Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.Type: GrantFiled: March 28, 2016Date of Patent: December 12, 2017Assignee: Intel CorporationInventors: Eric J. Li, Jimin Yao, Shawna M. Liff
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Publication number: 20170287735Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Applicant: Intel CorporationInventors: Jimin Yao, Eric Li, Shawna Liff