Abstract: Embodiments of the invention address deficiencies of the art in respect to memory fault tolerance, and provide a novel and non-obvious method, system and apparatus for single channel memory mirroring. In one embodiment of the invention, a single channel memory mirroring system can be provided. The single channel memory mirroring system can include a memory controller, a single communications channel, and an operational data portion of memory, and a duplicate data portion of memory, both portions being communicatively coupled to the memory controller over the single communications channel. Finally, the system can include single channel memory mirror logic. The logic can include program code enabled to mirror data in the operational data portion of memory in the duplicate data portion of memory.

Abstract: A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

Abstract: A memory module includes persistent-storage memory chips and an auxiliary voltage connector for powering the persistent-storage memory chips. An auxiliary power cable has a first end coupled to an electronic power source on the system board and has a second end having connector that plugs in to the auxiliary voltage connector on the memory module to provide power to the persistent-storage memory chips. The auxiliary power cable also resists movement of a latch lever to require disconnecting the auxiliary power cable before ejecting the memory module.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

Abstract: Computing devices have fan speeds governing airflows through the computing devices. The rack has a maximum airflow associated with a cooling component for the rack. The computing devices transmit their current airflows. A sum of the current airflows is determined. Where the sum is greater than the maximum airflow, the fan speeds of one or more selected computing devices are decreased. The fan speeds of lower priority computing devices may be reduced before the fan speeds higher priority computing devices are reduced. Fan speed reduction may be achieved in a centralized manner, by employing a centralized management component, or in a decentralized manner, without employing a centralized management component.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: An apparatus includes a socket that receives a memory module that includes a card having card edge voltage pads along the lower card edge, auxiliary voltage pads along at least one of the vertical card edges, and one or more persistent, solid-state memory chips on one or both card faces. A latch pivotally coupled to the socket is movable between a latched position and an unlatched position. The latch includes electrical latch contacts positioned for being engaged with the auxiliary voltage pads when that latch is in the latched position and being disengaged from the auxiliary voltage pads when the latch is in the unlatched position. The electrical latch contacts may provide a different voltage to the auxiliary voltage pads than the socket provides to the card edge voltage pads along the lower card edge.

Abstract: A memory module includes persistent-storage memory chips and an auxiliary voltage connector for powering the persistent-storage memory chips. An auxiliary power cable has a first end coupled to an electronic power source on the system board and has a second end having connector that plugs in to the auxiliary voltage connector on the memory module to provide power to the persistent-storage memory chips. The auxiliary power cable also resists movement of a latch lever to require disconnecting the auxiliary power cable before ejecting the memory module.

Abstract: An apparatus includes a socket that receives a memory module that includes a card having card edge voltage pads along the lower card edge, auxiliary voltage pads along at least one of the vertical card edges, and one or more persistent, solid-state memory chips on one or both card faces. A latch pivotally coupled to the socket is movable between a latched position and an unlatched position. The latch includes electrical latch contacts positioned for being engaged with the auxiliary voltage pads when that latch is in the latched position and being disengaged from the auxiliary voltage pads when the latch is in the unlatched position. The electrical latch contacts may provide a different voltage to the auxiliary voltage pads than the socket provides to the card edge voltage pads along the lower card edge.

Abstract: Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.

Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

Abstract: Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.