Abstract: A computer processing system includes a central processing unit (CPU) and logic instructions operable to, when a task ready to be scheduled for execution in the CPU (402) is the same as a task yielding to the task ready to be scheduled (406-Y), retain context information for the yielding task in background registers in the CPU, and move the context information for the yielding task directly from the background registers to foreground registers in the CPU for the task ready to be scheduled (410). The task ready to be scheduled is executed using the context information in the foreground registers (316).

Abstract: A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.

Abstract: A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.

Abstract: A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.

Abstract: A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more selected software-controllable interrupt types are determined. During execution of the test code, the MISR is used to also accumulate data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature. A test control register has a plurality of fields, each for selecting or not selecting a corresponding software-controllable interrupt type.

Abstract: For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.

Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.

Abstract: A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.

Abstract: A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more selected software-controllable interrupt types are determined. During execution of the test code, the MISR is used to also accumulate data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature. A test control register has a plurality of fields, each for selecting or not selecting a corresponding software-controllable interrupt type.

Abstract: A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled to receive test data directly from the plurality of test points, and a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result. In one aspect, the at least on staging storage element has a plurality of staging storage elements wherein each of the plurality of staging storage elements corresponds to a different pipeline stage of the data processing system. In another aspect the MISR result is independent of varying memory access times.

Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.

Abstract: A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.

Abstract: A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled to receive test data directly from the plurality of test points, and a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result. In one aspect, the at least on staging storage element has a plurality of staging storage elements wherein each of the plurality of staging storage elements corresponds to a different pipeline stage of the data processing system. In another aspect the MISR result is independent of varying memory access times.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is beings accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).