Data processing with configurable registers
A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.
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The present invention is related to the applications entitled:
-
- (1) “Method and Apparatus For Testing A Data Processing System” filed on Feb. 16, 2006 and having a U.S. Ser. No. of 11/355,681, now U.S. Pat. No. 7,444,568, and assigned to the same assignee as the present application; and
- (2) “Pipelined Processor With Deterministic Signature Generation” filed of even date herewith, U.S. Ser. No. 11/460,086, now U.S. Pat. No. 7,627,795, and assigned to the same assignee as the present application.
The present invention relates generally to data processors, and more particularly to testing a data processor.
BACKGROUND OF THE INVENTIONTesting of data processing systems is important to ensure proper operation. Testing may be performed in a factory following manufacture and prior to using the data processing system in a user application. The factory testing ensures an end user receives a properly functioning product. However, during operation of the data processing system by an end user, it may also be desirable to test the data processing system so that any failures which occur during normal operation of the product can be detected.
A well known technique to permit integrated circuits to be tested during operation is the use of logic testing registers, called Multiple Input Shift Register (MISR). Multiple input shift registers implement any of a variety of polynomials by receiving data from various internal nodes of the integrated circuit and performing signature compression and accumulation. The signature compression and accumulation is a series of logic operations which result in a single output value known as a signature value. The signature value is compared with a desired value to determine whether the integrated circuit being tested is functioning correctly.
Since the testing of the integrated circuit is performed on-line or while the integrated circuit is functioning in a real-world application, the circuitry for implementing the MISR and associated control must be implemented within the integrated circuit. Due to the size of a MISR and therefore expense, the number of MISRs and the implementation size of a MISR may be limited. As a result the ability to test the integrated circuit is severely limited.
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
DETAILED DESCRIPTIONIn operation, data processing system 10 is implemented as a pipelined data processing system. That means that the execution of data processing instructions functions in discrete time intervals in which a particular function in the execution occurs during each time interval. In one form, instruction execution advances in a pipeline in response to a system clock, wherein each cycle of the system clock advances the execution by one stage. In a first operation, an instruction is fetched in a first pipeline stage from the bus interface unit 14 by the instruction fetch unit 20. In a second pipeline stage, the fetched instruction is coupled to the instruction decoder 18 from the instruction fetch unit 20 and decoded. The resulting decoded instruction is then coupled to execution units 16 and instruction execution begins in a third pipeline stage. In some forms, the instruction execution occurs during two cycles of the system clock. In one form, the execution stage of the pipeline has two phases of instruction execution. Depending upon the functionality of the executed instruction, the result of the pipelined operation may be fed back to the input of the pipeline and used as a subsequent input. In a final stage of the pipeline a write back to memory, such as the cache 30, is performed. The various pipeline stages which are described herein are defined herein as “staging”. In other words, staging is the operation of data processing system in specific stages each having a predetermined function or functions. Staging is also the association of specific hardware circuitry with the functions of each stage in the ordered sequence which forms the data processing pipeline.
Registers files 22 are shared between the load/store unit 28 and the execution units 16. The load/store unit 28 operates in response to the global control 24 and provides data to and receives data from the bus interface unit 14. The load/store unit 28 also provides data to and receives data from the general purpose registers within the register files 22. Exception logic 26 functions to generate any of various types of data processing exceptions. An interrupt request may be generated and provided to the exception logic 26 in response to various events either within the illustrated data processing system 10 or from sources external to the data processing system 10. For example, instruction execution latency resulting from the generation of wait states may cause the generation of an exception as well as the occurrence of faults resulting from instruction execution errors. Various types of real-time interrupt requests may also be received by exception logic 26 via one or more interrupt request inputs.
The discussion of the operation of data processing system 10 to this point is conventional. Additionally, data processing system 10 has a real-time test capability that permits testing of various test points located at predetermined circuit nodes within the functional circuitry of data processing system. For example, the various test points may be located within any or all of the functional blocks illustrated in
A MISR functions to receive test data from various test locations within the system as the system is exercised. The MISR compresses the multiple test values by performing a plurality of predetermined logic operations that are determined by which test polynomial is selected. The compressed MISR result is typically referred to as a MISR signature. The value of the MISR signature and the structure of the MISR itself are polynomial specific and test point specific, and will vary from implementation to implementation. After exercising the system for a predetermined interval, the MISR result is compared with an expected MISR value for the implemented polynomial and a determination is made whether the data processing system is working correctly based on the comparison. Multiple MISR registers may be implemented to allow for a larger number of test points to be captured for signature generation. The advantage in increasing the number of MISRs is to allow for broader test coverage but comes at the penalty of additional size and cost of the system. Further explanation below is required to appreciate how the configurable registers within register files 22 provide the ability to dually use storage devices in data processing system 10 for normal operation and for test without negatively impacting the size of the system.
Illustrated in
Referring to
Illustrated in
During execution of testing code when data processing system 10 is in the test mode, the subset of GPRs that is dedicated for MISR functionality is typically unavailable for use as general purpose registers. Therefore, the selection of which general purpose registers to implement the enhanced MISR functionality is made to ensure that no essential processor capability is lost. Therefore proper selection of a subset of general purpose registers will be discussed.
Illustrated in
It should be noted also that the registers which are selected as being configurable may still be used in the test mode of operation as general purpose source registers. In other words, these registers may function normally as source operands to instructions. The values that are in the flip-flops of the bit cells 60-64 of the registers configured as MISRs during test mode provide a useful source of pseudo-random source values or test vectors for exercising logic within the data processing system. Since the MISRs are accumulating as execution proceeds, pseudo-random values are continuously generated. Therefore, during the test mode at least one register in the portion of the GPRs that are configured as one or more MISRs is used as a source register for a processor instruction that is executed by data processing system 10. In one form, that processor instruction performs an operation such as an arithmetic operation, a logic operation or an effective address calculation.
Illustrated in
Such register usage conventions are well known and serve to promote interoperability of different compiled software functions. Proper selection of the GPRs to be used as MISR registers during the test mode is thus critical to minimize the impact on the calling convention and interoperability. It should be noted that the test mode relies on execution of normal software functions to provide the stimulus to the data processing system, and that the test data values which are accumulated into one or more MISR signature values are generated as a result of normal execution of normal, not special, processor instructions using the instructions available to the user outside of the test mode of operation, and for the most part using the same ABI conventions on general purpose register usage.
Illustrated in
By now it should be appreciated that there has been provided a method of operation and a data processing system that has configurable MISR capability for a portion of a general purpose register file. It should be understood that the portion may vary from a small subset of the general purpose register files to a substantial portion of the general purpose register files. The readily configurable MISR registers discussed herein satisfy a customer requirement that a data processing system be available for processing to meet system needs in safety applications and to ensure that critical applications are not interrupted. The configurable test capability disclosed herein provides a low cost and flexible method of adding signature test logic to a data processing system. Size is minimized by the time multiplexed use of a portion of the general purpose registers for this function.
In one form there is herein provided a method of providing a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for a data processing system. A test mode is entered. During the test mode, a portion of the plurality of GPRs is configured to operate as at least one multiple input shift register (MISR). During the test mode, each register in the portion of the plurality of GPRs generates a signature. The test mode is exited. After exiting the test mode, the portion of the plurality of GPRs is used as general purpose registers for normal program execution. In one form the portion of the plurality of GPRs is configured to operate as at least one MISR by implementing one or more bit cells of each register in the portion of the plurality of general purpose registers with at least one logic gate. During the test mode, the at least one logic gate receives a first input from another bit cell and the at least one logic gate provides an output to yet another bit cell. Test data is provided from test points located at predetermined circuit nodes within the data processing system to a second input of the at least one logic gate. In one form the portion of the plurality of GPRs corresponds to a selected subset of registers of the plurality of GPRs. In another form the selected subset of registers is selected based on a software Application Binary Interface (ABI). In yet another form the portion of the plurality of GPRs corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of GPRs. In another form remaining bit locations within each register of the selected subset of registers of the plurality of GPRs continue to operate as general purpose registers for normal program execution during the test mode. In yet another form the subset of bit locations corresponds to higher order bit locations within the each register of the selected subset of registers of the plurality of GPRs. In another form during test mode, at least one register in the portion of GPRs configured as the at least one MISR is used as a source register for a processor instruction executed by the data processing system. In another form the processor instruction performs an operation selected from a group consisting of an arithmetic operation, a logic operation, or an effective address calculation.
In another form there is provided a data processing system having functional circuitry which performs at least one data processing function. A register file is coupled to the functional circuitry and has a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system. A portion of the plurality of GPRs is reconfigurable as at least one test register during a test mode. Control circuitry provides a test enable indicator to the register file, wherein the portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In another form the portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from the predetermined circuit nodes within the functional circuitry and generates a signature used to test functionality of the functional circuitry. In another form the at least one test register is at least one multiple input shift register (MISR). In another form the register file further includes selecting circuitry coupled to each bit cell in each register of the portion of the plurality of GPRs. The selecting circuitry selects between providing a normal write input and providing a test input. In another form the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled. In yet another form the portion of the plurality of GPRs corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of GPRs. In another form remaining bit locations within each register of the selected subset of registers of the plurality of GPRs continue to operate as general purpose registers for normal program execution during the test mode.
Also there is provided a data processing system having functional circuitry which performs at least one data processing function. A register file has a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system. A portion of the plurality of GPRs are reconfigurable as at least one multiple input shift register (MISR) during a test mode. Control circuitry provides a test enable indicator to the register file, wherein each register in the portion of the plurality of GPRs, in response to the test enable indicator indicating that the test mode is enabled, operates as a multiple input shift register (MISR) to generate a signature based on test data received from predetermined circuit nodes within the functional circuitry. In another form the register file has selecting circuitry for each bit cell in each register of the portion of the plurality of general purpose registers. The selecting circuitry selects between providing a normal write input and providing a test input based at least in part on the test data received from the predetermined circuit nodes within the functional circuitry. A logic gate is in each bit cell in each register of the portion of the plurality of general purpose registers. Each logic gate is coupled to receive at least a portion of the test data from the predetermined circuit nodes within the functional circuitry and coupled to provide the test input to the selecting circuitry. In another form the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled. In another form the portion of the plurality of GPRs corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of GPRs.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. It should be understood that all circuitry described herein may be implemented either in silicon or another semiconductor material or alternatively by software code representation of silicon or another semiconductor material. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
Claims
1. In a data processing system, a method comprising:
- providing a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system;
- entering a test mode;
- during the test mode, configuring a portion of the plurality of general purpose registers to operate as at least one multiple input shift register (MISR) wherein a portion of a register line is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation;
- during the test mode, each register in the portion of the plurality of general purpose registers generating a signature;
- exiting the test mode; and
- after exiting the test mode, using the portion of the plurality of general purpose registers as general purpose registers for normal program execution.
2. The method of claim 1, wherein the configuring the portion of the plurality of general purpose registers to operate as at least one MISR comprises:
- implementing one or more bit cells of each register in the portion of the plurality of general purpose registers with at least one logic gate wherein, during the test mode, the at least one logic gate receives a first input from another bit cell and the at least one logic gate provides an output to yet another bit cell; and
- providing test data from test points located at predetermined circuit nodes within the data processing system to a second input of the at least one logic gate.
3. The method of claim 1, wherein the portion of the plurality of general purpose registers correspond to a selected subset of registers of the plurality of general purpose registers.
4. The method system of claim 3, wherein the selected subset of registers is selected based on a software Application Binary Interface (ABI).
5. The method of claim 1, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.
6. The method of claim 5, wherein remaining bit locations within each register of the selected subset of registers of the plurality of general purpose registers continue to operate as general purpose registers for normal program execution during the test mode.
7. The method of claim 5, wherein the subset of bit locations corresponds to higher order bit locations within the each register of the selected subset of registers of the plurality of general purpose registers.
8. The method of claim 1, further comprising:
- during test mode, using at least one register in the portion of general purpose registers configured as the at least one MISR as a source register for a processor instruction executed by the data processing system.
9. The method of claim 8, wherein the processor instruction performs an operation selected from a group consisting of an arithmetic operation, a logic operation, or an effective address calculation.
10. A data processing system, comprising:
- functional circuitry which performs at least one data processing function;
- a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, wherein a portion of the plurality of general purpose registers are reconfigurable as at least one test register during a test mode, a portion of a register line of the at least one test register is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation; and
- control circuitry which provides a test enable indicator to the register file, wherein the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operate to accumulate test data from predetermined circuit nodes within the functional circuitry.
11. The data processing system of claim 10, wherein the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from the predetermined circuit nodes within the functional circuitry and generate a signature used to test functionality of the functional circuitry.
12. The data processing system of claim 10, wherein the at least one test register comprises at least one multiple input shift register (MISR).
13. The data processing system of claim 10, wherein the register file further comprises:
- selecting circuitry coupled to storage circuitry in each register of the portion of the plurality of GPRs, the selecting circuitry selecting between providing a normal write input to the storage circuitry and providing a test input based at least in part on the test enable indicator.
14. The data processing system of claim 13, wherein the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled.
15. The data processing system of claim 10, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.
16. The data processing system of claim 15, wherein remaining bit locations within each register of the selected subset of registers of the plurality of general purpose registers continue to operate as general purpose registers for normal program execution during the test mode.
17. A data processing system, comprising:
- functional circuitry which performs at least one data processing function;
- a register file having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, wherein a portion of the plurality of general purpose registers are reconfigurable as at least one multiple input shift register (MISR) during a test mode, a portion of a register line of the plurality of general purpose registers is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation; and
- control circuitry which provides a test enable indicator to the register file, wherein each register in the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operates as at least a portion of a multiple input shift register (MISR) to generate a signature based on test data received from predetermined circuit nodes within the functional circuitry.
18. The data processing system of claim 17, wherein the register file comprises:
- selecting circuitry for each bit cell in each register of the portion of the plurality of general purpose registers, the selecting circuitry selecting between providing a normal write input and providing a test input based at least in part on the test data received from the predetermined circuit nodes within the functional circuitry; and
- a logic gate in each bit cell in each register of the portion of the plurality of general purpose registers, each logic gate coupled to receive at least a portion of the test data from the predetermined circuit nodes within the functional circuitry and coupled to provide the test input to the selecting circuitry.
19. The data processing system of claim 18, wherein the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled.
20. The data processing system of claim 17, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.
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Type: Grant
Filed: Jul 26, 2006
Date of Patent: Oct 26, 2010
Patent Publication Number: 20080126769
Assignee: Freescale Semiconductor, Inc. (Austin, TX)
Inventors: William C. Moyer (Dripping Springs, TX), Jimmy Gumulja (Austin, TX)
Primary Examiner: Kevin L Ellis
Assistant Examiner: Guerrier Merant
Attorney: Robert L. King
Application Number: 11/460,090
International Classification: G01R 31/28 (20060101); G01R 31/26 (20060101); G11C 29/00 (20060101);