Patents by Inventor Jinan Lin
Jinan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10030822Abstract: Disclosed is a solar spectrum type LED type eye-protection flat lamp, comprising: a front diffusion panel, a front grating panel, a circuit board, a rear reflection and diffusion panel, a multicolor LED lamp bead group and an annular reflector. The front grating panel is snugly attached to the front diffusion panel and is arranged on a concave disk at the light-emitting side of the LED eye-protection flat lamp, and the front diffusion panel is arranged in front of the front grating panel; the rear reflection and diffusion panel is snugly attached to the circuit board and is arranged on a back-side concave disk of the LED eye-protection flat lamp, and the reflection and diffusion panel is arranged in front of the circuit board.Type: GrantFiled: January 7, 2013Date of Patent: July 24, 2018Inventors: Jinan Lin, Jinbiao Lin
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Publication number: 20150338033Abstract: Disclosed is a solar spectrum type LED type eye-protection flat lamp, comprising: a front diffusion panel, a front grating panel, a circuit board, a rear reflection and diffusion panel, a multicolor LED lamp bead group and an annular reflector. The front grating panel is snugly attached to the front diffusion panel and is arranged on a concave disk at the light-emitting side of the LED eye-protection flat lamp, and the front diffusion panel is arranged in front of the front grating panel; the rear reflection and diffusion panel is snugly attached to the circuit board and is arranged on a back-side concave disk of the LED eye-protection flat lamp, and the reflection and diffusion panel is arranged in front of the circuit board.Type: ApplicationFiled: January 7, 2013Publication date: November 26, 2015Inventors: Jinan LIN, Jinbiao LIN
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Patent number: 8209523Abstract: A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.Type: GrantFiled: January 22, 2009Date of Patent: June 26, 2012Assignee: Intel Mobile Communications GmbHInventors: Ulf Nordqvist, Jinan Lin, Xiaoning Nie, Stefan Maier, Siegmar Koeppe
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Patent number: 8108862Abstract: The invention relates to a device to be used with a thread scheduling method, and to a thread scheduling method comprising the steps of performing a scheduling for threads to be executed by a multithreaded (MT) processor (11), characterized in that the scheduling is performed as a function of a variable (idle) representing the processor idle time.Type: GrantFiled: December 12, 2005Date of Patent: January 31, 2012Assignee: Infineon Technologies AGInventors: Lorenzo Di Gregorio, Jinan Lin
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Patent number: 8077644Abstract: A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.Type: GrantFiled: July 20, 2007Date of Patent: December 13, 2011Assignee: Infineon Technologies AGInventors: Jinan Lin, Xiaoning Nie, Ralf Itjeshorst, Tilman Giese, Xianming Deng, Denny Brem, Klaus Mott, Tideya Kella
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Patent number: 8046487Abstract: In order to be able to use a smaller routing table (4) and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table (4) so as to find a correspondence between the destination address identifier and one of the entries of the routing table (4). Each entry of the routing table (4) corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier.Type: GrantFiled: August 5, 2003Date of Patent: October 25, 2011Assignee: Infineon Technologies AGInventors: Sankar Narayan Jagannathan, Xiaoning Nie, Jinan Lin
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Publication number: 20100185832Abstract: A system and method for processing data is disclosed. In one embodiment, a data moving processor comprises a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.Type: ApplicationFiled: January 22, 2009Publication date: July 22, 2010Inventors: Ulf Nordqvist, Jinan Lin, Xiaoning Nie, Stefan Maier, Siegmar Koppe
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Patent number: 7590117Abstract: An arrangement and a method for processing data of multiprotocol data packets comprises at least one multiplexer connected to input ports; at least one first programmable data processing unit configured to provide header words and into payload words; a buffer management unit configured to generate localization data which specifies a corresponding memory area of the payload memory; a descriptor generator unit for generating data packet descriptors; a RISC processor configured to generate, in dependence on the data packet descriptors, header data for transmit data packets and payload processing instructions for processing data of the data packet payload words, stored in the payload memory, of the associated received data packet; and at least one second programmable data processing unit configured to process the payload words from the payload memory in accordance with the payload processing instructions and assembles the payload words with the header data to form transmit data packets.Type: GrantFiled: December 23, 2003Date of Patent: September 15, 2009Assignee: Infineon Technologies AGInventors: Lorenzo Di Gregorio, Jinan Lin, Xiaoning Nie, Thomas Wahl
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Publication number: 20090119460Abstract: Methods, apparatuses, and software for storing a first portion of a data transfer descriptor in cached address space, and storing a second portion of the data transfer descriptor in uncached address space. Also, methods, apparatuses, and software for reading at least a portion of a data transfer descriptor from cached address space, initiating a memory transfer based on the data transfer descriptor, and storing a parameter indicating a status of the data transfer descriptor in uncached address space.Type: ApplicationFiled: November 7, 2007Publication date: May 7, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Jinan Lin, Xiaoning Nie, Stefan Maier
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Patent number: 7526636Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).Type: GrantFiled: November 12, 2004Date of Patent: April 28, 2009Assignee: Infineon Technologies AGInventors: Lajos Gazsi, Jinan Lin, Soenke Mehrgardt, Xiaoning Nie
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Publication number: 20090022077Abstract: A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.Type: ApplicationFiled: July 20, 2007Publication date: January 22, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Jinan LIN, Xiaoning NIE, Ralf ITJESHORST, Tilman GIESE, Xianming DENG, Denny BREM, Klaus MOTT, Tideya KELLA
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Patent number: 7457294Abstract: In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where t?[1, . . . , T] and D is the smallest common multiple of t?[1, . . . , T].Type: GrantFiled: October 27, 2005Date of Patent: November 25, 2008Assignee: Infineon Technologies AGInventors: Jinan Lin, Sankamarayan Jagannathan, Xiaoning Nie
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Patent number: 7263604Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p? [1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q? [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t? [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).Type: GrantFiled: February 24, 2005Date of Patent: August 28, 2007Assignee: Infineon Technologies AGInventors: Lajos Gazsi, Jinan Lin, Soenke Mehrgardt, Xiaoning Nie
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Publication number: 20070101109Abstract: A processor comprises checking and control devices, first register, and register bank. The control device checks a condition or a subcondition of the condition within a first time unit based on a first subcondition checked within a second time unit preceding the first time unit, a second subcondition checked within a third time unit preceding the second time unit, and a single condition. The first register is coupled to the control device for storing the checked condition and the output of the first register is coupled to the control device for providing the stored, checked subcondition as a checked, first subcondition. The input of the register bank is coupled to the first register for receiving the stored, checked subcondition, the second register stores the received, checked subcondition as the checked, second subcondition, and the register bank is coupled to the control device for providing the checked, second subcondition.Type: ApplicationFiled: October 20, 2006Publication date: May 3, 2007Applicant: Infineon Technologies AGInventors: Xiaoning Nie, Jinan Lin
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Publication number: 20060156306Abstract: The invention relates to a device to be used with a thread scheduling method, and to a thread scheduling method comprising the steps of performing a scheduling for threads to be executed by a multithreaded (MT) processor (11), characterized in that the scheduling is performed as a function of a variable (idle) representing the processor idle time.Type: ApplicationFiled: December 12, 2005Publication date: July 13, 2006Applicant: INFINEON TECHNOLOGIES AGInventors: Lorenzo Di Gregorio, Jinan Lin
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Publication number: 20060106940Abstract: In order to be able to use a smaller routing table (4) and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table (4) so as to find a correspondence between the destination address identifier and one of the entries of the routing table (4). Each entry of the routing table (4) corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier.Type: ApplicationFiled: August 5, 2003Publication date: May 18, 2006Applicant: Infineon Technologies AGInventors: Sankar Jagannathan, Xiaoning Nie, Jinan Lin
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Publication number: 20060104277Abstract: In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where t?[1, . . . , T] and D is the smallest common multiple of t?[1, . . . , T].Type: ApplicationFiled: October 27, 2005Publication date: May 18, 2006Applicant: Infineon Technologies AGInventors: Jinan Lin, Sankamarayan Jagannathan, Xiaoning Nie
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Publication number: 20050198476Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).Type: ApplicationFiled: November 12, 2004Publication date: September 8, 2005Applicant: Infineon Technologies AGInventors: Lajos Gazsi, Jinan Lin, Soenke Mehrgardt, Xiaoning Nie
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Publication number: 20050193186Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p?[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q?[1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t?[1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).Type: ApplicationFiled: February 24, 2005Publication date: September 1, 2005Inventors: Lajos Gazsi, Jinan Lin, Soenke Mehrgardt, Xiaoning Nie
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Publication number: 20050160254Abstract: A multithread processor based on the inventive architecture is a clocked multithread processor (1) for data processing of N threads by means of a standard processor root unit (2), wherein a thread Tj which is to be processed at any given time by the standard processor root unit (2) can be switched without any clock cycle loss by means of a switching trigger signal (UTS) to another thread T1, wherein the switching trigger signal (UTS) is generated as a consequence of a program instruction (which is fetched from a program instruction memory (3) and implies a latency time) for the thread Tj which is to be processed at that time and results in a latency time for the standard processor root unit (2), before the program instruction which has been fetched and implies a latency time is decoded by the standard processor root unit (2).Type: ApplicationFiled: December 17, 2004Publication date: July 21, 2005Applicant: Infineon Technologies AGInventors: Jinan Lin, Xiaoning Nie