Abstract: A surface plasmon resonance imaging apparatus is provided. The surface plasmon resonance imaging apparatus includes a light irradiation unit configured to irradiate polarized light onto a metal coating film provided on one surface of a prism, a light modulator configured to spatially pattern-encode light reflected by the metal coating film and the prism, a light detector configured to detect a pattern-encoded light signal, obtained through pattern-encoding by the light modulator, as a spectral signal, a signal processor configured to spatially decode the spectral signal and analyze a decoded spectral signal to generate characteristic data of a sample provided on the metal coating film, and an output unit configured to output the characteristic data of the sample as a two-dimensional (2D) image.

Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Abstract: A semiconductor light-emitting device includes a laminated semiconductor structure having a first surface and a second surface opposing each other, a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively forming the first surface and the second surface, and an active layer. First and second electrodes are disposed on the first surface of the laminated semiconductor structure and the second surface of the laminated semiconductor structure, respectively. A connecting electrode extends to the first surface to be connected to the second electrode. A support substrate is disposed on the second electrode, and an insulating layer insulates the connecting electrode from the active layer and the first conductivity-type semiconductor layer.

Abstract: A semiconductor light-emitting device includes a laminated semiconductor structure having a first surface and a second surface opposing each other, a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively forming the first surface and the second surface, and an active layer. First and second electrodes are disposed on the first surface of the laminated semiconductor structure and the second surface of the laminated semiconductor structure, respectively. A connecting electrode extends to the first surface to be connected to the second electrode. A support substrate is disposed on the second electrode, and an insulating layer insulates the connecting electrode from the active layer and the first conductivity-type semiconductor layer.

Abstract: A method of grinding a substrate is provided. A substrate including a first main surface having a semiconductor layer formed thereon and a second main surface opposed to the first main surface is prepared. A support film is attached to the first main surface using a glue. The second main surface of the substrate is ground so as to reduce a thickness of the substrate. The support film is removed from the first main surface by applying force to the support film in a non-traverse direction.

Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Abstract: A method of grinding a substrate is provided. A substrate including a first main surface having a semiconductor layer formed thereon and a second main surface opposed to the first main surface is prepared. A support film is attached to the first main surface using a glue. The second main surface of the substrate is ground so as to reduce a thickness of the substrate. The support film is removed from the first main surface by applying force to the support film in a non-traverse direction.

Abstract: There is provided a method of manufacturing a substrate for mounting an electronic device. The method includes disposing a protective layer on a surface of the substrate except for an edge portion thereof . An oxide film is disposed on the entirety of the surface of the substrate except for where the protective layer is disposed The oxide film is grown. A through hole is formed in a thickness direction of the substrate by selectively etching the protective layer. The oxide film is removed. In the manufacturing method, defects in the substrate for mounting an electronic device may be reduced and manufacturing costs can be reduced.

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract: Methods of forming integrated circuit substrates include forming first and second trenches having unequal widths in a semiconductor substrate and then depositing a first oxide layer at a first temperature into the first and second trenches. The first oxide layer has a thickness sufficient to completely fill the first trench but only partially fill the second trench, which is wider than the first trench. A step is also performed to selectively remove a portion of the first oxide layer from a bottom of the second trench. A second oxide layer is then deposited at a second temperature onto the bottom of the second trench. The second temperature is greater than the first temperature. For example, the first temperature may be in a range from about 300° C. to about 460° C. and the second temperature may be in a range from about 500° C. to about 600° C.

Abstract: Disclosed are chamber inserts and apparatuses using the chamber inserts. A chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, a first protruding portion extending outwardly from a first portion of the cylindrical body portion, the first portion positioned circumferentially along the cylindrical body portion and a second protruding portion extending outwardly from a second portion of the cylindrical body portion, the second portion positioned circumferentially along less than all of the cylindrical body portion. In another example, the chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, the cylindrical body portion including a slit and at least one hole, the slit and the at least one hole positioned circumferentially along the cylindrical body portion and a first protruding portion extending outwardly from a first portion of the cylindrical body portion.

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

Abstract: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.

Abstract: Provided are a method of forming a device isolation layer and a method of fabricating a semiconductor device. The method includes: forming a first trench and a second trench in a substrate, wherein the second trench is connected to the first trench and has a width smaller than the first trench; forming a liner insulation layer in the second trench such that the liner insulation layer is buried in the second trench; and forming a gap fill insulation layer on the liner insulation layer such that the gap fill insulation layer is buried in the first trench.

Abstract: In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.

Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.