Abstract: An apparatus that is capable of detecting the presence of a plug comprising: a plurality of receptacles configured to receive a plurality of prongs from a plug, wherein the plurality of receptacles includes a first receptacle and a second receptacle; a controller configured to detect whether a first prong of the plurality of prongs is present in the first receptacle; and a switch configured to provide power to the second receptacle. The switch provides power to the second receptacle when the controller detects that the first prong of the plurality of prongs is present in the first receptacle and the switch does not provide power to the second receptacle when the controller does not detect that the first prong is present in the first receptacle.

Abstract: An invention is provided for encouraging routine testing for TDS levels in a liquid. The invention includes determining a TDS level of the liquid utilizing an apparatus capable of determining a TDS level based on the conductivity of the liquid. Next, corrective action can be performed to reduce the TDS level when the TDS level is beyond a predetermined level. To facilitate a continual visual reminder for future TDS level testing, the apparatus is removably attached to a surface viewable when in proximity of a device utilized to access the liquid utilizing an integrated attachment mechanism.

Abstract: An invention is provided for encouraging routine testing for TDS levels in a liquid. The invention includes a conductivity sensor capable of sensing a conductivity level of a liquid, and a processor in electrical communication with the conductivity sensor. The processor has logic that calculates a TDS level for the liquid based on the conductivity level of the liquid. The calculated TDS level for the liquid is then displayed on a display in electrical communication with the processor. Also included is a speaker, which is electrical communication with the processor. To provide automatic reminders to the user, an integrated timing mechanism is included that is in communication with the processor. When a predetermined period of time has elapsed, such as the period of time between periodic TDS level testing, the integrated timing mechanism sends a signal to the processor to provide an alert to the user to test the TDS level.

Abstract: Concerning raster converter circuit on HDTV, this invention is used to store datas to frame memory when datas converted into block unit on digital HDTV shall be displayed and also used as address generator in order to convert data format into raster scan method through frame memory when, by using blocktransform including DCT, VQ etc., data format with raster scan method from camera shall be displayed on screen with making up data by block unit which is convenient to condense data through frame memory, and can be applicable for all systems using blocktransform of DCT, VQ etc., i.e. HDTV, ATV, MPEG, JPEG & Videophone etc.

Abstract: A memory address and display control apparatus for an high definition television comprising a memory address controller for controlling memory read/write addresses in response to a motion vector and a control signal, the memory address controller having a display read control circuit, a motion compensation read control circuit, and a raster format write control circuit, a memory unit having a previous frame memory for storing a video signal of a previous frame and a present frame memory for storing a video signal of a present frame, a multiplexing circuit for 2 to 1-multiplexing the output addresses from the memory address controller to alternately address the previous frame memory and the present frame memory in the memory unit, an input/output controller for controlling data input/output of the memory unit in response to frame and invert frame signals, a display controller for receiving video data from the memory unit under the control of the input/output controller and displaying the received video data, a

Abstract: A vascular graft fabricated of a polyester fiber, the surface of which is impregnated with biodegradable blood-compatible materials, characterized in that the surface of the said vascular graft comprises carboxylate groups and is impregnated with polysaccharides or their derivatives. The vascular graft is manufactured by treating the hydrophobic surface of a vascular graft fabricated of a polyester fiber to render it more hydrophilic and then impregnating the vascular graft with above polysaccharides or their derivatives by chelate bond with metal ions or physical adsorption in order to increase the adhesion properties and adding glycerin to the impregnated polysaccharides or their derivatives in order to increase the softness so that the impregnated substances may turn into the state of gel by blood at the time of use.

Abstract: A novel E. coli strain which can produce L-phenylalanine and is resistant to high osmotic pressure and a process for producing L-phenylalanine by use of the novel E. coli (KCCM 10,016) are disclosed.

Abstract: A control system for automatically controlling the operation of actuators of an excavator.

Abstract: An automatic actuating system for actuators of excavator. The system of this invention automatically controls the bucket which is overloaded to be free from the overloaded state thereof, the bucket to maintain an angular position with respect to the absolute line of the ground surface so as to prevent the objects contained in the bucket from being dropped, the bucket cylinder and the boom cylinder to accomplish the desired surface finishing operation by handling for the dipper cylinder, actuators to limit the operational ranges thereof, optimal quantity of hydraulic fluid flow of the main hydraulic pumps for respective actuators, and the pre-running for the actuators.

Abstract: The DRAM cell of the invention comprises a structure wherein a deep trench is formed on a silicon wafer, a stacked trench capacitor is formed around a silicon pillar associated with the trench, and a vertical transfer transistor is formed on top of the silicon pillar after the formation of the stacked trench capacitor. The transfer transistor is connected to the storage capacitor through a selectively doped n.sup.+ diffused layer, and isolation between DRAM cells is formed by the trench.

Abstract: The invention relates to a method of manufacturing a DRAM in which a storage capacitor is stacked vertically over a switching junction FET.

Abstract: A method for manufacturing a DRAM cell is provided having an isolation merged trench for applying to 16 megabit and 64 megabit DRAM cells, which includes the steps forming a primary dielectric for a capacitor within the interior of a trench, depositing an n.sup.+ doped polysilicon, forming a secondary dielectric and then stacking polysilicon thereon and connecting the polysilicon within an n.sup.+ diffusion layer of the bottom of the trench for forming a plate. As a result of this method all of the capacitors disposed between the n.sup.+ polysilicon storing electrode and the n.sup.+ polysilicon plate as well as the polysilicon storing electrode and the n.sup.+ diffusion layer plate are utilized as a storing capacitor.

Abstract: A DRAM cell of a stack structure having a cup-shaped polysilicon storage electrode for being applied to a 16 mega and 64 mega DRAM wherein a transfer transistor is firstly manufactured, a bit line is formed, an oxide film grid is formed between the cell and cell in the minimum design rule, and upon completing this, the polysilicon storage electrode is formed into a single or double cup shape, whereby the capacitor area is remarkably increased when compared with the conventional stacked structure DRAM cell so that the area efficiency is greatly increased and the process can be executed by such a mask number as the prior stacked structure mask layer number and the structure thereof is simple.