Abstract: A three-dimensional memory device includes a plurality of row lines stacked alternately with a plurality of interlayer dielectric layers in a vertical direction on a substrate, and each of the plurality of row lines having a projection from a side surface thereof; and a plurality of vias extending in the vertical direction from the substrate, each coupled to the projection of a corresponding row line, and electrically coupling the plurality of row lines to a peripheral circuit defined below the substrate.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

Abstract: The present disclosure relates to KINIZ alloys having a homogeneous microstructure. A KINIZ alloy includes: copper (Cu) and iron (Fe) in a total amount of 75 wt % to 95 wt %; and nickel (Ni) in an amount of 1 wt % to 20 wt %, zirconium (Zr) in an amount of 0.1 wt % to 5.0 wt %, and a balance of inevitable impurities. A KINIZ alloy includes: copper (Cu) and iron (Fe) in a total amount of 75 wt % to 95 wt %; and manganese (Mn) in an amount of 2.0 wt % to 5.0 wt %, zirconium (Zr) in an amount of 0.3 wt % to 1.0 wt %, and a balance (excluding 0%) of inevitable impurities.

Abstract: A method for analyzing face information in an electronic device is provided. The method includes detecting at least one face region from an image that is being captured by a camera module, zooming in the at least one detected face region, and analyzing the at least one detected and zoomed in face region according to at least one analysis item.

Abstract: A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.

Abstract: An apparatus and a method for controlling driving of a vehicle may include a first sensor that detects whether an accelerator pedal is pressed, a second sensor that detects a number of RPM of an engine, and a controller that determines whether the vehicle coasts based on whether the accelerator pedal is pressed, and determines whether to change a gear ratio of a transmission based on the number of RPM of the engine so that the coasting distance is increased in the coasting deceleration section, improving the fuel efficiency.

Abstract: A transmission for an electric vehicle may include a first planetary gear set; a first motor configured to input power to a first rotation element of the first planetary gear set; a differential configured to receive power output from a second rotation element of the first planetary gear set; a second motor configured to selectively provide power to a third rotation element of the first planetary gear set; a second planetary gear set including a first rotation element which is directly connected to the differential, and a second rotation element which is configured to selectively receive power from the second motor; and a third planetary gear set including a third rotation element which is directly connected to a third rotation element of the second planetary gear set, a second rotation element which is fixed, and a first rotation element which is directly connected to a selected output shaft of the differential.

Abstract: A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.

Abstract: A powertrain for an electric vehicle includes: a planetary gear having a first rotating element, a second rotating element, and a third rotating element, wherein a first rotating element is connected to a first shaft and the second rotating element is connected to a second shaft; a first motor configured to selectively supply power to the first shaft at two or more gear ratios; a first shift assembly configured to transfer power of the first motor to the first shaft through one of two or more external engagement gear trains having different gear ratios; and a second motor configured to selectively supply power to the first shaft and the second shaft. The third shaft is fixedly disposed on a transmission housing, and any two shafts among the first, second and third shafts restrain each other.

Abstract: A three-dimensional semiconductor memory device may include a cell wafer including a source plate, a plurality of first word lines stacked to be spaced apart from one another along a plurality of first vertical channels projecting from a bottom surface of the source plate in a vertical direction, and a plurality of second word lines stacked to be spaced apart from one another along a plurality of second vertical channels projecting from a top surface of the source plate in a vertical direction; a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first row decoder unit which transfers an operating voltage to the plurality of first word lines; and a second peripheral wafer bonded to a top surface of the cell wafer, and including a second row decoder unit which transfers an operating voltage to the plurality of second word lines.

Abstract: A powertrain for an electric vehicle includes: a planetary gear including a first rotating element, a second rotating element, and a third rotating element, where the first rotating element is connected to a first shaft, the second rotating element is connected to a second shaft, and the third rotating element is selectively connected to a transmission housing; a first motor supplying power to the first shaft at all times; and a second motor selectively supplying power to the first shaft and the second shaft. Two rotating elements among the first, second, third rotating elements of the planetary gear are selectively connected to integrally rotate the entire planetary gear.

Abstract: A powertrain for an electric vehicle includes: a planetary gear including a first rotating element, a second rotating element, and a third rotating element, where the first rotating element is connected to a first shaft, the second rotating element is connected to a second shaft, and the third rotating element is connected to a third shaft; a first motor supplying power to the first shaft at all times; and a second motor selectively supplying power to the first shaft and the second shaft. The third shaft is fixedly connected to a transmission housing, and any two shafts among the first, second and third shafts restrain each other.

Abstract: An engine glow plug disconnection detection method may include: increasing, by a controller, temperature of a plurality of glow plugs by performing a rapid temperature increase mode when an engine start signal of a vehicle is recognized by the controller; determining whether the glow plugs are disconnected and the number of disconnections using an engine start early-stage voltage of the vehicle and a voltage of the vehicle when the rapid temperature increase mode is performed, by the controller; recognizing, by the controller, cylinders of an engine with at least a disconnected glow plug upon determining that one or more glow plugs are disconnected: and storing, by the controller, a number of disconnected glow plugs and information related to corresponding cylinders.

Abstract: A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

Abstract: A planetary gear set may include a first rotation element fixedly connected to a first shaft, a second rotation element fixedly connected to a second shaft, and a third rotation element fixedly connected to a third shaft; a first motor which is mounted to supply power to the first shaft continuously; and a second motor which is mounted to supply power to the second shaft continuously, and the third shaft is connected to be selectively connectable to a transmission housing, and any two shafts of the first shaft, the second shaft, and the third shaft are configured to constrain rotations thereof to each other.

Abstract: Provided are battery management apparatuses and methods. The battery management apparatus includes a sensitivity determiner configured to determine sensitivity of a battery state based on sensed battery information and previous battery state information, and an execution parameter adjuster configured to adjust a parameter for estimating the battery state based on the determined sensitivity of the battery state.

Abstract: A semiconductor memory device includes a cell region defined with vertical channels which pass through electrode layers and interlayer dielectric layers alternately stacked; a step region disposed adjacent to the cell region in a first direction, and defined with contacts coupled to the electrode layers extending in different lengths; a first opening passing through the electrode layers and the interlayer dielectric layers in the step region; a second opening passing through the electrode layers and the interlayer dielectric layers in the cell region; under wiring lines coupled with a peripheral circuit defined on a substrate; top wiring lines disposed over the electrode layers and the interlayer dielectric layers, and coupled with the contacts; and vertical vias coupling the under and top wiring lines, wherein the vertical vias include first vertical vias which pass through the first opening and second vertical vias which pass through the second opening.

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.

Abstract: A compressive sensing image sensor includes: a pixel array; and a readout circuit configured to receive pixel data on a shot image in an analogue form, and to process the pixel data, wherein the pixel array includes a plurality of blocks each having a plurality of pixels and arranged in an array form, wherein the circuit includes: a compressive sensing multiplexer to which a plurality of pixel data outputted from a corresponding block from among the plurality of blocks are inputted; an LFSR configured to arbitrarily select at least one pixel data from the plurality of pixel data inputted to the compressive sensing multiplexer; and a delta-sigma ADC configured to receive the at least one pixel data selected by the LFSR, to delta-sigma modulate the received at least one pixel data, and to generate compressive sensing data for restoring an image of the corresponding block from among the shot images.

Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.