Abstract: A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.

Abstract: A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output node, the first driver configured to output a first data strobe signal to the first input/output node during a write operation; and a first receiver coupled to receive a second data strobe signal from the first input/output node and output a third data strobe signal during a read operation when the data strobe buffer is in a first or second mode, the first receiver configured to compare the second data strobe signal with a first reference voltage and output a result of the comparison as the third data strobe signal when the data strobe buffer is in the first mode, the receiver further configured to not compare the second data strobe signal with the first reference voltage when the data strobe buffer is in the second mode.

Abstract: The detachable electric headrest includes a headrest pole, an ascending and descending slider, elastic pins, and locking bars. The headrest pole is configured such that engaging depressions are formed in the lower end portion thereof. The ascending and descending slider is provided with detachment depressions, into which the respective lower end portions of the headrest pole are inserted, and is mounted to the fastening bracket of a seat frame so as to be raised and lowered. The elastic pins are mounted in the respective detachment depressions so as to be inserted into the engaging depressions of the inserted headrest pole. The locking bars are configured such that cut depressions, in which the elastic pins can be moved, are formed in respective upper ends thereof, and are configured to be elastically supported to the ascending and descending slider.

Abstract: An apparatus for locking a table of a seat back to selectively secure the table in multiple stages, may include a base, a shaft coupled to the base and the table, an actuating arm fastened to the shaft and rotatable with the shaft, the actuating arm having actuating gear teeth, a locking arm rotatably provided on the base, wherein the locking arm includes locking gear teeth and the locking gear teeth is selectively engaged with the actuating gear teeth by the actuating arm such that when the actuating arm is rotated in a forward direction, the actuating gear teeth is engaged with the locking gear teeth or pass over the locking gear teeth according to rotational degree of the actuating arm, and a locking arm holding unit co-axially coupled with the actuating arm to the base and selectively activated by the actuating arm.

Abstract: The detachable electric headrest includes a headrest pole, an ascending and descending slider, elastic pins, and locking bars. The headrest pole is configured such that engaging depressions are formed in the lower end portion thereof. The ascending and descending slider is provided with detachment depressions, into which the respective lower end portions of the headrest pole are inserted, and is mounted to the fastening bracket of a seat frame so as to be raised and lowered. The elastic pins are mounted in the respective detachment depressions so as to be inserted into the engaging depressions of the inserted headrest pole. The locking bars are configured such that cut depressions, in which the elastic pins can be moved, are formed in respective upper ends thereof, and are configured to be elastically supported to the ascending and descending slider.

Abstract: A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output node, the first driver configured to output a first data strobe signal to the first input/output node during a write operation; and a first receiver coupled to receive a second data strobe signal from the first input/output node and output a third data strobe signal during a read operation when the data strobe buffer is in a first or second mode, the first receiver configured to compare the second data strobe signal with a first reference voltage and output a result of the comparison as the third data strobe signal when the data strobe buffer is in the first mode, the receiver further configured to not compare the second data strobe signal with the first reference voltage when the data strobe buffer is in the second mode.

Abstract: A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n?1]) within the embedded clock data signal.

Abstract: A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.

Abstract: Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal.

Abstract: A low voltage data transmitting circuit (LVDTC) may be connected to a first transmission line that transmits a first voltage signal to a receiver and a second transmission line that transmits a second voltage signal to the receiver. The LVDTC includes a first resistor coupled to the first transmission line, a second resistor coupled to the second transmission line, and a control unit coupled to the first transmission line and the second transmission line, the control unit being configured to control voltage levels of the first and second voltage signals such that the voltage levels of the first and second voltage signals are higher than a ground voltage level of the receiver, wherein the first and second voltage signals may constitute a differential pair.

Abstract: A digital circuit such as a level shifter circuit includes a current mirror having first and second current supply transistors configured to provide an output signal to an output node based on an input signal. A leakage current control circuit is configured to maintain the first and second current supply transistors in an off state in response to the output signal. An output compensation circuit coupled to the output node is configured to maintain a voltage level of the output node based on a level of output signal.

Abstract: A data communication system includes a host configured to transmit a power-down identifier through a data channel and configured to drive a strobe channel. A client is coupled to the host through the data channel and the strobe channel, wherein the client is configured to drive the data channel to wake up the host; enter a power-down state in response to the power-down identifier received from the host; and wake up by detecting whether the strobe channel is driven by the host.

Abstract: Level shifter circuits include zero threshold transistors that reduce a voltage seen by a switching transistor of the level shifter circuits and may increase blocking of static current in the level shifter circuit. The zero threshold transistors are controlled based on the input to the level shifter circuit. Thin oxide transistors may be used to provide low threshold voltages for the switching transistors. Additional level shifter circuits include serially connected zero threshold transistors that act as switching transistors in a current mirror or latch-type level shifter circuit.

Abstract: A digital circuit such as a level shifter circuit includes a current mirror having first and second current supply transistors configured to provide an output signal to an output node based on an input signal. A leakage current control circuit is configured to maintain the first and second current supply transistors in an off state in response to the output signal. An output compensation circuit coupled to the output node is configured to maintain a voltage level of the output node based on a level of output signal.

Abstract: Level shifter circuits include zero threshold transistors that reduce a voltage seen by a switching transistor of the level shifter circuits and may increase blocking of static current in the level shifter circuit. The zero threshold transistors are controlled based on the input to the level shifter circuit. Thin oxide transistors may be used to provide low threshold voltages for the switching transistors. Additional level shifter circuits include serially connected zero threshold transistors that act as switching transistors in a current mirror or latch-type level shifter circuit.

Abstract: In a clock squarer having a semiconductor chip pad and a square wave generating circuit, the clock squarer can generate a square wave having stable duty, irrespective of variation in temperature, process or supply voltage. In the clock squarer, a capacitor is provided between the chip pad and the square wave generating circuit. The clock squarer in accordance with the present invention is especially applicable to processes that involve high leakage current or a fabrication process for products requiring high-speed operation.

Abstract: An impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor is provided. Since the impedance control circuit does not use an external resistor for impedance matching, the PCB size can be reduced. In particular, a controllable current source matches the impedance more precisely compared to the external resistor.

Abstract: An impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor is provided. Since the impedance control circuit does not use an external resistor for impedance matching, the PCB size can be reduced. In particular, a controllable current source matches the impedance more precisely compared to the external resistor.

Abstract: A fermentation process for preparing a high yield erythritol using a salt tolerant mutant of Candida sp. [Candida magnoliae SR101:KCCM-10160]. More specifically, the present invention relates to a process for preparing erythritol under optimal fermentation conditions for maximal erythritol production by optimizing the environmental conditions of culture, including medium component, pH, temperature, aeration rate and agitation speed.

Abstract: A fermentation process for preparing a high yield erythritol using a salt tolerant mutant of Candida sp. [Candida magnoliae SR101:KCCM-10160]. More specifically, the present invention relates to a process for preparing erytlritol under optimal fermentation conditions for maximal erythritol production by optimizing the environmental conditions of culture, including medium component, pH, temperature, aeration rate and agitation speed.