Abstract: Disclosed herein are an apparatus and method for processing vehicle data security based on a cloud.

Abstract: An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Abstract: An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Abstract: A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.

Abstract: A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.

Abstract: A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.

Abstract: A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.

Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Abstract: A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

Abstract: A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Abstract: A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

Abstract: A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

Abstract: At least one magnetic nanowire including multiple cells; a write-read head combined with a first contact of the magnetic nanowire; and a read-only head combined with a second contact of the magnetic nanowire. Data stored through a write head included in the write-read head are read in sequence through a read head included in the write-read head in response to a last in first out (LIFO) method.

Abstract: At least one magnetic nanowire including multiple cells; a write-read head combined with a first contact of the magnetic nanowire; and a read-only head combined with a second contact of the magnetic nanowire. Data stored through a write head included in the write-read head are read in sequence through a read head included in the write-read head in response to a last in first out (LIFO) method.

Abstract: A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

Abstract: A phase detection circuit is configured to generate a phase detection signal by comparing a divided clock signal obtained by dividing a first clock signal to a second clock signal during a deactivation period of a control signal, and generate the phase detection signal by comparing the first and second clock signals during an activation period of the control signal.

Abstract: A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.

Abstract: A phase detection circuit is configured to generate a phase detection signal by comparing a divided clock signal obtained by dividing a first clock signal to a second clock signal during a deactivation period of a control signal, and generate the phase detection signal by comparing the first and second clock signals during an activation period of the control signal.

Abstract: An internal clock signal generation circuit includes a variable delay line unit including an initial variable delayer having an initial delay amount controlled based on condition information and configured to delay an input clock signal by a time corresponding to a delay control signal to output a delay locked loop (DLL) clock signal, a delay replica modeling unit configured to delay the DLL clock signal by a time obtained by modeling a clock delay component and output a feedback clock signal, and a phase comparison unit configured to compare a phase of the input clock signal with a phase of the feedback clock signal and generate the delay control signal.