Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

Abstract: A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.

Abstract: An internal clock signal generation circuit includes a variable delay line unit including an initial variable delayer having an initial delay amount controlled based on condition information and configured to delay an input clock signal by a time corresponding to a delay control signal to output a delay locked loop (DLL) clock signal, a delay replica modeling unit configured to delay the DLL clock signal by a time obtained by modeling a clock delay component and output a feedback clock signal, and a phase comparison unit configured to compare a phase of the input clock signal with a phase of the feedback clock signal and generate the delay control signal.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: A fuse apparatus for controlling a built-in self stress unit includes a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended, and a fuse configured to record an operation state of the built-in self stress according to the one-cycle end signal. A method for controlling a built-in self stress includes repeatedly generating any stress test mode, in a test mode counting the generated stress test pattern, and activating a cycle end signal when a counting value reaches a predetermined value, and recording an operation state of the built-in self stress in a fuse on the basis of the counted value.

Abstract: A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.

Abstract: A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: A delay locked loop circuit includes: a voltage level detector for detecting of an external power source voltage level; a phase comparator for comparing phases of reference clock and feedback clock; a clock delayer for designating one of a first delay cell unit and a second delay cell unit as initial delay cell unit and the other as connected delay cell unit, delaying the reference clock by the initial delay cell unit until delay amount of the reference clock reaches a predetermined delay amount, delaying the reference clock by the connected delay cell unit after the delay amount of the reference clock reaches the predetermined delay amount in response to an output signal of the phase comparator, and outputting a delay locked clock; and a delay duplication modeler for changing the delay locked clock to reflect an actual delay condition of the reference clock and outputting the feedback clock.

Abstract: A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.

Abstract: Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal.

Abstract: A delay locked loop circuit includes: a voltage level detector for detecting of an external power source voltage level; a phase comparator for comparing phases of reference clock and feedback clock; a clock delayer for designating one of a first delay cell unit and a second delay cell unit as initial delay cell unit and the other as connected delay cell unit, delaying the reference clock by the initial delay cell unit until delay amount of the reference clock reaches a predetermined delay amount, delaying the reference clock by the connected delay cell unit after the delay amount of the reference clock reaches the predetermined delay amount in response to an output signal of the phase comparator, and outputting a delay locked clock; and a delay duplication modeler for changing the delay locked clock to reflect an actual delay condition of the reference clock and outputting the feedback clock.

Abstract: A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.

Abstract: A semiconductor memory device adjusts an activation timing and pulse width of a pin strobe signal according to a power supply voltage variation, and thereby loads data on a pipelatch properly and prevents an activation period of a pin strobe signal from falling out of a period for valid data. The semiconductor memory device includes a voltage detector configured to detect a level of a power supply voltage to output a detection signal, a pin strobe signal transfer path configured to transfer a pin strobe signal determining an input timing of data to a pipelatch, a delay controller configured to control a delay value of the pin strobe signal transfer path in response to the detection signal, and a pulse width modulator configured to modulate a pulse width of the pin strobe signal in response to the detection signal.

Abstract: A multi-port memory device includes a plurality ports, a plurality of banks, a plurality of global data buses, first and second I/O controllers, and a test input/output (I/O) controller. The ports perform a serial I/O data transmission. The banks perform a parallel I/O data transmission with the ports. The global data buses are employed for transmitting data between the ports and the banks. The first I/O controller controls a serial data transmission between the ports and external devices. The second I/O controller controls a parallel data transmission between the ports and the global buses. The test I/O controller generates test commands based on a test command/address (C/A) inputted from the external devices and transmits a test I/O data with the global data bus during a test operation mode.

Abstract: A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.