Abstract: A memory device using a phase change material and a method for forming the same are disclosed. One embodiment of a memory device includes a first insulating layer provided on a substrate and defining an opening; a first conductor including a first portion and a second portion, the first portion provided on a bottom of the opening, the second portion being continuously provided along a sidewall of the opening; a variable resistor connected to the second portion of the first conductor and provided along the sidewall of the opening; and a second conductor provided on the variable resistor.

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. Formation of an integrated circuit memory cell include forming a first electrode on a substrate. An insulation layer is formed on the substrate with an opening that exposes at least a portion of a first electrode. An amorphous variable resistivity material is formed on the first electrode and extends away from the first electrode along sidewalls of the opening. A crystalline variable resistivity material is formed in the opening on the amorphous variable resistivity material. A second electrode is formed on the crystalline variable resistivity material.

Abstract: A method of forming a thin film including zirconium titanium oxide including introducing a reactant including a mixture of a zirconium precursor and a titanium precursor onto a substrate, and introducing an oxidizing agent onto the substrate to form a solid material including zirconium titanium oxide on the substrate is provided. The thin film may be applied to a gate insulation layer of the gate structure, a dielectric layer of the capacitor or a flash memory device, and methods of forming the same are provided.

Abstract: A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.

Abstract: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.

Abstract: A phase-changeable layer and a method of forming the same are disclosed. In the method, a first hydrogen gas is introduced into a reaction chamber into which a substrate is loaded at a first flow rate to form first plasma. A primary cyclic CVD process is carried out using precursors in the reaction chamber to form a lower phase-changeable layer having a first grain size on the substrate. A second hydrogen gas is introduced into the reaction chamber at a second flow rate less than the first flow rate to form second plasma. A secondary cyclic CVD process is carried out using the precursors in the reaction chamber to form an upper phase-changeable layer having a second grain size smaller than the first grain size on the substrate, thereby forming a phase-changeable layer. Thus, the phase-changeable layer may have strong adhesion strength with respect to a lower layer and good electrical characteristics.

Abstract: In one embodiment, a phase change memory device includes an insulation structure over a substrate. The insulation structure ahs an opening defined therethrough. A first layer pattern is formed on sidewalls and a bottom of the opening. A second layer pattern is formed on the first layer pattern and substantially fills the opening.

Abstract: A germanium (Ge) compound is provided. The Ge compound has a chemical formula GeR1xR2y. “R1” is an alkyl group, and “R2” is one of hydrogen, amino group, allyl group and vinyl group. “x” is greater than zero and less than 4, and the sum of “x” and “y” is equal to 4. Methods of forming the Ge compound, methods of fabricating a phase change memory device using the Ge compound, and phase change memory devices fabricated using the Ge compound are also provided.

Abstract: A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups “—N?C?O”, “—N?C?S”, “—N?C?Se”, “—N?C?Te”, “—N?C?Po” and “—C?N”.

Abstract: A multilayer electrode structure has a conductive layer including aluminum, an oxide layer formed on the conductive layer, and an oxygen diffusion barrier layer. The oxide layer includes zirconium oxide and/or titanium oxide. The oxygen diffusion barrier layer is formed at an interface between the conductive layer and the oxide layer by re-oxidizing the oxide layer. The oxygen diffusion barrier layer includes aluminum oxide.

Abstract: A method of forming a phase change material layer includes preparing a substrate having an insulator and a conductor, loading the substrate into a process housing, injecting a deposition gas into the process housing to selectively form a phase change material layer on an exposed surface of the conductor, and unloading the substrate from the process housing, wherein a lifetime of the deposition gas in the process housing is shorter than a time the deposition gas takes to react by thermal energy.

Abstract: A gap filling method and a method for forming a memory device, including forming an insulating layer on a substrate, forming a gap region in the insulating layer, and repeatedly forming a phase change material layer and etching the phase change material layer to form a phase change material layer pattern in the gap region.

Abstract: Methods of forming MIM comprise forming a lower electrode on a semiconductor substrate, forming a lower dielectric layer on the lower electrode, and forming an upper dielectric layer on the lower dielectric layer. The lower dielectric layer may be formed of dielectrics having larger energy band gap than that of the upper dielectric layer. An upper electrode is formed on the upper dielectric layer. The upper electrode may be formed of a metal layer having a higher work function than that of the lower electrode.

Abstract: A method of fabricating a phase-change random-access memory (RAM) device includes forming a chalcogenide material on a substrate. A bottom contact is formed under the chalcogenide material, the bottom contact comprising TiAlN. Forming the bottom contact includes performing an atomic layer deposition (ALD) process, the ALD process including introducing an NH3 source gas into a chamber in which the ALD process is being carried out, a flow amount of the NH3 gas being such that the resulting bottom contact has a chlorine content of less than 1 at %. The bottom contact can include TiAlN having a crystallinity in terms of full-width half-maximum (FWHM) of less than about 0.65 degree.

Abstract: A phase changeable material layer usable in a semiconductor memory device and a method of forming the same are disclosed.

Abstract: A unit cell structure in a non-volatile semiconductor device includes a lower electrode. The variable resistor is formed on the lower electrode and includes a first insulation thin film, a third insulation thin film, and a second insulation thin film located between the first and third insulation thin films. A breakdown voltage of the second insulation thin film is lower than respective breakdown voltages of the first and third insulation thin films. An upper electrode is formed on the variable resistor.

Abstract: An integrated circuit device is formed by providing a substrate and forming a capacitor on the substrate. The capacitor includes a lower electrode disposed on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric. A hydrogen barrier insulation layer is formed on the upper electrode and a hydrogen barrier spacer is formed on a sidewall of the capacitor.

Abstract: In a method of manufacturing a capacitor including a hemispherical grain (HSG) silicon layer, after forming a storage electrode electrically coupled to a contact region of a substrate, the HSG silicon layer is formed on the storage electrode by providing a first gas including silicon and a second gas onto a surface of the storage electrode with a volume ratio of about 1.0:0.1 to about 1.0:5.0. A dielectric layer and a plate electrode are sequentially formed on the HSG silicon layer. A grain size of the HSG silicon layer may be easily adjusted and abnormal growths of the HSG at a lower portion of the storage electrode may be suppressed. Therefore, the HSG silicon layer may be uniformly formed on the storage electrode, and a structural stability of the storage electrode may be improved to prevent electrical defects of the capacitor.

Abstract: Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).

Abstract: Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.