Patents by Inventor Jin K. Kim
Jin K. Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7433381Abstract: A long wavelength vertical cavity surface emitting laser having a substrate, a first mirror situated on the substrate, an active region situated on the first mirror, a second mirror situated on the active region. The first mirror may have several pairs of layers with an oxidized layer in one or more pairs of that mirror. The substrate may include InP and the mirror components may be compatible with the InP. The one or more layers in the first mirror may be oxidized via a trench-like approach or other arrangement.Type: GrantFiled: June 25, 2003Date of Patent: October 7, 2008Assignee: Finisar CorporationInventors: Tzu-Yu Wang, Hoki Kwon, Jae-Hyun Ryou, Gyoungwon Park, Jin K. Kim
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Patent number: 7391799Abstract: A vertical cavity surface emitting laser with a mode-selective mirror. A filter is formed on the top DBR stack of a VCSEL. The filter includes semiconductor layers that are etch stops for immediately superior layers. The filter is selectively etched to create a first region that is phase matched to the top DBR stack and a second region that is phase mismatched to the top DBR stack. The second region inhibits undesired modes and provides additional absorption for the undesired modes. The first region is formed using a wet-etch process whose etch depth is controlled because the semiconductor layers are etch stops for immediately superior layers.Type: GrantFiled: July 7, 2005Date of Patent: June 24, 2008Assignee: Finisar CorporationInventors: James A. Cox, Jin K. Kim, Gyoungwon Park
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Patent number: 7286584Abstract: A vertical cavity surface emitting laser (VCSEL) structure includes a bottom distributed Bragg reflector (DBR) arranged over a substrate; a metal layer interposed between the bottom DBR and the substrate, wherein the metal layer and bottom DBR form a composite mirror structure. A patterned dielectric layer may be interposed between the metal layer and the bottom DBR to reduce a deleterious chemical reaction between the metal layer and the bottom DBR. The metal layer directly contacts a portion of the bottom DBR to enhance the electrical and thermal conductivity of the VCSEL structure.Type: GrantFiled: December 8, 2004Date of Patent: October 23, 2007Assignee: Finisar CorporationInventors: Tzu-Yu Wang, Jin K. Kim, Hoki Kwon, Gyoungwon Park, Jae-Hyun Ryou
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Patent number: 7255746Abstract: MBE nitrogen sources of dimethylhydrazine, tertiarybutlyhydrazine, nitrogentrifloride, and NHx radicals. Those nitrogen sources are beneficial in forming nitrogen-containing materials on crystalline subtrates using MBE. Semiconductor lasers in general, and VCSEL in particular, that have nitrogen-containing layers can be formed using such nitrogen sources.Type: GrantFiled: September 4, 2002Date of Patent: August 14, 2007Assignee: Finisar CorporationInventors: Ralph H. Johnson, Jin K. Kim, James K. Guenter
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Patent number: 7170916Abstract: DBR mirrors, and vertical cavity surface emitting lasers that incorporate such mirrors, comprised of stacked, multiple levels of different materials having different etching rates for a selected etchant and etching method. Such DBRs are fabricated by etching an upper level(s) down to a lower level(s) to form a pillar or trenched structure, beneficially having an aperture, that has predetermined optical characteristics. When part of a vertical cavity surface emitting laser, a lower level can include an ion-implanted region that optionally extends into an active region and into a bottom DBR.Type: GrantFiled: October 30, 2002Date of Patent: January 30, 2007Assignee: Finisar CorporationInventor: Jin K. Kim
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Patent number: 7099362Abstract: A vertical cavity surface emitting laser (VCSEL) includes a substrate; a first mirror stack over the substrate; an active region having a plurality of quantum wells over the first mirror stack; a tunnel junction over the active region, the tunnel junction including a modulation-doped layer; and a second mirror stack over the tunnel junction. The modulation doped layer can be used for either the n-layer or the p-layer, or the both layers of the tunnel junction. Such tunnel junctions are especially useful for a long wavelength VCSEL.Type: GrantFiled: November 14, 2003Date of Patent: August 29, 2006Assignee: Finisar CorporationInventor: Jin K. Kim
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Patent number: 7087726Abstract: The present invention relates generally to the generation and characterization of neutralizing anti-IFN-? monoclonal antibodies with broad reactivity against various IFN-? subtypes. The invention further relates to the use of such anti-IFN-? antibodies in the diagnosis and treatment of disorders associated with increased expression of IFN-?, in particular, autoimmune disorders such as insulin-dependent diabetes mellitus (IDDM) and systemic lupus erythematosus (SLE).Type: GrantFiled: January 9, 2002Date of Patent: August 8, 2006Assignee: Genentech, Inc.Inventors: Anan Chuntharapai, Jin K. Kim, Leonard G. Presta, Timothy Stewart
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Patent number: 7085298Abstract: A vertical cavity surface emitting laser (VCSEL) includes a substrate; a first mirror stack over the substrate; an active region having a plurality of quantum wells over the first mirror stack; a tunnel junction over the active region, a p-layer of the tunnel junction including GaPSb or AlGaPSb; and a second mirror stack over the tunnel junction. The p-layer including GaPSb or AlGaPSb can be used to form a tunnel junction with an n-doped layer of InP or AlInAs, or with a lower bandgap material such as InGaAs, AlInGaAs or InGaAsP. Such tunnel junctions are especially useful for a long wavelength VCSEL.Type: GrantFiled: October 31, 2003Date of Patent: August 1, 2006Assignee: Finisar CorporationInventor: Jin K. Kim
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Patent number: 7054345Abstract: A vertical cavity surface emitting laser having an oxidizable layer oxidized with enhanced lateral oxidation. The oxidation may involve adding oxygen in the form of a fluid, with or without other fluid such as water vapor, in the oxidizing environment, and/or in the layer to be oxidized. This oxidation approach may be used for layers with relatively low aluminum content such as in InP based structures, or with high aluminum content such as in GaAs based structures.Type: GrantFiled: June 27, 2003Date of Patent: May 30, 2006Assignee: Finisar CorporationInventors: Jae-Hyun Ryou, Tzu-Yu Wang, Jin K. Kim, Gyoungwon Park, Hoki Kwon
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Patent number: 6987791Abstract: Long-wavelength VCSELs having top DBR mirrors with multiple levels. The individual levels of the DBR are comprised of different materials. The top DBR mirror level(s) forms a pillar structure and/or are defined by trenches. Top contacts are formed on the top DBR mirror below that mirror's top level. An aperture is formed in one of the DBR layers. An ion implanted region is formed in the top DBR and may extend into the active region and into part of a bottom DBR. The top DBRs are beneficially fabricated by etching parts of upper level(s) down to the lower level(s).Type: GrantFiled: October 30, 2002Date of Patent: January 17, 2006Assignee: Finisar CorporationInventor: Jin K. Kim
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Publication number: 20040264541Abstract: A long wavelength vertical cavity surface emitting laser having a substrate, a first mirror situated on the substrate, an active region situated on the first mirror, a second mirror situated on the active region. The first mirror may have several pairs of layers with an oxidized layer in one or more pairs of that mirror. The substrate may include InP and the mirror components may be compatible with the InP. The one or more layers in the first mirror may be oxidized via a trench-like approach or other arrangement.Type: ApplicationFiled: June 25, 2003Publication date: December 30, 2004Applicant: Honeywell International Inc.Inventors: Tzu-Yu Wang, Hoki Kwon, Jae-Hyun Ryou, Gyoungwon Park, Jin K. Kim
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Publication number: 20040264531Abstract: A vertical cavity surface emitting laser having an oxidizable layer oxidized with enhanced lateral oxidation. The oxidation may involve adding oxygen in the form of a fluid, with or without other fluid such as water vapor, in the oxidizing environment, and/or in the layer to be oxidized. This oxidation approach may be used for layers with relatively low aluminum content such as in InP based structures, or with high aluminum content such as in GaAs based structures.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Applicant: Honeywell International Inc.Inventors: Jae-Hyun Ryou, Tzu-Yu Wang, Jin K. Kim, Gyoungwon Park, Hoki Kwon
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Publication number: 20040086016Abstract: Long-wavelength VCSELs having top DBR mirrors with multiple levels. The individual levels of the DBR are comprised of different materials. The top DBR mirror level(s) forms a pillar structure and/or are defined by trenches. Top contacts are formed on the top DBR mirror below that mirror's top level. An aperture is formed in one of the DBR layers. An ion implanted region is formed in the top DBR and may extend into the active region and into part of a bottom DBR. The top DBRs are beneficially fabricated by etching parts of upper level(s) down to the lower level(s).Type: ApplicationFiled: October 30, 2002Publication date: May 6, 2004Inventor: Jin K. Kim
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Publication number: 20040086013Abstract: DBR mirrors, and vertical cavity surface emitting lasers that incorporate such mirrors, comprised of stacked, multiple levels of different materials having different etching rates for a selected etchant and etching method. Such DBRs are fabricated by etching an upper level(s) down to a lower level(s) to form a pillar or trenched structure, beneficially having an aperture, that has predetermined optical characteristics. When part of a vertical cavity surface emitting laser, a lower level can include an ion-implanted region that optionally extends into an active region and into a bottom DBR.Type: ApplicationFiled: October 30, 2002Publication date: May 6, 2004Inventor: Jin K. Kim
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Publication number: 20040040495Abstract: MBE nitrogen sources of dimethylhydrazine, tertiarybutlyhydrazine, nitrogentrifloride, and NHx radicals. Those nitrogen sources are beneficial in forming nitrogen-containing materials on crystalline subtrates using MBE. Semiconductor lasers in general, and VCSEL in particular, that have nitrogen-containing layers can be formed using such nitrogen sources.Type: ApplicationFiled: September 4, 2002Publication date: March 4, 2004Inventors: Ralph H. Johnson, Jin K. Kim, James K. Guenter
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Publication number: 20030166228Abstract: The present invention relates generally to the generation and characterization of neutralizing anti-IFN-&agr; monoclonal antibodies with broad reactivity against various IFN-&agr; subtypes. The invention further relates to the use of such anti-IFN-&agr; antibodies in the diagnosis and treatment of disorders associated with increased expression of IFN-&agr;, in particular, autoimmune disorders such as insulin-dependent diabetes mellitus (IDDM) and systemic lupus erythematosus (SLE).Type: ApplicationFiled: January 9, 2002Publication date: September 4, 2003Inventors: Anan Chuntharapai, Jin K. Kim, Leonard G. Presta, Timothy Stewart
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Publication number: 20020075926Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.Type: ApplicationFiled: August 21, 2001Publication date: June 20, 2002Inventors: Larry A. Coldren, Eric M. Hall, Jin K. Kim, Shigeru Nakagawa
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Patent number: 5546341Abstract: A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage.Type: GrantFiled: May 15, 1995Date of Patent: August 13, 1996Assignee: Samsung Electronics Co., Ltd.Inventors: Kang D. Suh, Jin K. Kim, Jeong H. Choi
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Patent number: 5541879Abstract: A nonvolatile semiconductor memory device according to the present invention includes an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. The nonvolatile semiconductor memory device operates in a program mode, a program verify mode and a read mode. A current source provides a predetermined electrical current to the bit lines during both data reading and programming modes, and a common data latch stores program data during a write operation, as well as senses and stores data when the nonvolatile memory device is operated in a data read mode and a program verify mode.Type: GrantFiled: May 15, 1995Date of Patent: July 30, 1996Assignee: Samsung Electronics Co., Ltd.Inventors: Kang D. Suh, Jin K. Kim, Jeong H. Choi
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Patent number: 5473563Abstract: A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage.Type: GrantFiled: December 22, 1993Date of Patent: December 5, 1995Assignee: Samsung Electronics Co., Ltd.Inventors: Kang D. Suh, Jin K. Kim, Jeong H. Choi