Patents by Inventor Jin-Ki Jung
Jin-Ki Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120009757Abstract: A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jin-Ki JUNG
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Patent number: 8049196Abstract: A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.Type: GrantFiled: December 12, 2008Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Publication number: 20110256354Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jin-Ki JUNG
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Patent number: 8026557Abstract: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer.Type: GrantFiled: October 14, 2008Date of Patent: September 27, 2011Assignee: Hynix Semiconductor, Inc.Inventor: Jin-Ki Jung
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Publication number: 20110207305Abstract: A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Inventor: Jin-Ki JUNG
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Patent number: 7994061Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.Type: GrantFiled: June 30, 2008Date of Patent: August 9, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Patent number: 7964914Abstract: A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers.Type: GrantFiled: June 30, 2008Date of Patent: June 21, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Patent number: 7960265Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.Type: GrantFiled: June 15, 2010Date of Patent: June 14, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Publication number: 20110110581Abstract: Disclosed herein is a three-dimensional (3D) object recognition system and method. The 3D object recognition system includes a storage unit for storing an extended randomized forest in which a plurality of randomized trees is included and each of the randomized trees includes a plurality of leaf nodes, training means for extracting a plurality of keypoints from a training target object image, and calculating and storing an object recognition posterior probability distribution and training target object-based keypoint matching posterior probability distributions, and matching means for extracting a plurality of keypoints from a matching target object image, matching the extracted keypoints to a plurality of leaf nodes, recognizing an object using the object recognition posterior probability distributions, and matching the keypoints to keypoints of the recognized object using training target object-based keypoint matching posterior probability distributions stored at the matched leaf nodes.Type: ApplicationFiled: October 26, 2010Publication date: May 12, 2011Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hyun Seung YANG, Kyu Sung CHO, Jae Sang YOO, Jin Ki JUNG
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Publication number: 20110076851Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jin-Ki JUNG
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Patent number: 7915120Abstract: Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes.Type: GrantFiled: April 29, 2009Date of Patent: March 29, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jung-Woo Park, Jin-Ki Jung, Kwon Hong, Ki-Seon Park
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Patent number: 7867913Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.Type: GrantFiled: September 25, 2008Date of Patent: January 11, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Publication number: 20100248434Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.Type: ApplicationFiled: June 15, 2010Publication date: September 30, 2010Inventor: Jin-Ki Jung
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Patent number: 7754592Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.Type: GrantFiled: June 29, 2007Date of Patent: July 13, 2010Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Publication number: 20100062581Abstract: Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes.Type: ApplicationFiled: April 29, 2009Publication date: March 11, 2010Applicant: Hynix Semiconductor Inc.Inventors: Jung-Woo PARK, Jin-Ki JUNG, Kwon HONG, Ki-Seon PARK
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Publication number: 20090250679Abstract: A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.Type: ApplicationFiled: December 12, 2008Publication date: October 8, 2009Applicant: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Publication number: 20090162794Abstract: A method for fabricating a semiconductor device is provided. The method includes forming an even number of first hard mask patterns over an etch target layer, forming sacrificial patterns on sidewalls of the first hard mask patterns and forming second hard mask patterns on sidewalls of the sacrificial patterns. The second hard mask patterns are formed to have a first space between the first hard mask patterns. The etch target layer is etched by using the first and the second hard mask patterns.Type: ApplicationFiled: June 30, 2008Publication date: June 25, 2009Applicant: Hynix Semiconductor Inc.Inventor: Jin-Ki JUNG
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Publication number: 20090163011Abstract: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.Type: ApplicationFiled: June 30, 2008Publication date: June 25, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jin-Ki JUNG
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Publication number: 20090159563Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.Type: ApplicationFiled: June 30, 2008Publication date: June 25, 2009Applicant: Hynix Semiconductor Inc.Inventor: Jin-Ki JUNG
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Publication number: 20090159965Abstract: A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers.Type: ApplicationFiled: June 30, 2008Publication date: June 25, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jin-Ki JUNG