Patents by Inventor Jin Onuki
Jin Onuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230246111Abstract: A wide gap semiconductor device has a wide gap semiconductor layer 10; and a metal electrode 20 disposed on the wide gap semiconductor layer 10. The metal electrode 20 has a monocrystalline layer 21 having a hexagonal close-packed (HCP) structure in an interface region between the metal electrode 20 and the wide gap semiconductor layer 10. The monocrystalline layer 21 has a specific element-containing region 22 containing O, S, P or Se.Type: ApplicationFiled: August 25, 2021Publication date: August 3, 2023Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke MAEYAMA, Shunichi NAKAMURA, Jin ONUKI
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Publication number: 20230042772Abstract: A wide gap semiconductor device has: a wide gap semiconductor layer; and a metal layer 20 provided on the wide gap semiconductor layer. The metal layer 20 has a single crystal layer 21 in an interface region at an interface with the wide gap semiconductor layer. When it is assumed that a lattice constant, in an equilibrium state, of a metal constituting the metal layer 20 is L, the single crystal layer 21 in the interface region includes a first region in which a lattice constant L1 is smaller than L by 1.5% to 8%.Type: ApplicationFiled: March 23, 2021Publication date: February 9, 2023Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke MAEYAMA, Shunichi NAKAMURA, Jin ONUKI
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Patent number: 7141741Abstract: A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.Type: GrantFiled: September 22, 2003Date of Patent: November 28, 2006Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Publication number: 20040056349Abstract: A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.Type: ApplicationFiled: September 22, 2003Publication date: March 25, 2004Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Publication number: 20030016502Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements beingType: ApplicationFiled: March 20, 2002Publication date: January 23, 2003Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Patent number: 6434008Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements beingType: GrantFiled: August 27, 1998Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Patent number: 6353258Abstract: A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the units are arranged in the same direction on the substrate, and all of the units are electrically connected with electrode terminal feet, and the electrode terminal feet are electrically connected with linkage terminal foot. The electrode terminal feet are disposed with a certain interval.Type: GrantFiled: June 26, 2000Date of Patent: March 5, 2002Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Hirokazu Inoue, Ryuichi Saito, Mutsuhiro Mori, Yasutoshi Kurihara, Jin Onuki, Shin Kimura, Satoshi Shimada, Kazuhiro Suzuki, Yukio Kamita, Isao Kobayashi, Kazuji Yamada, Naohiro Momma
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Patent number: 6225598Abstract: In a method for high frequency pulse welding and an apparatus therefor, a highly directive arc can be obtained by eliminating the effect of the inductance of the welding cable, which tends to make the high frequency electromagnetic pinch force large. In a method and an apparatus for high frequency pulse arc welding which is performed by generating an arc between an inconsumable electrode or a consumable electrode arranged near a portion of a base metal to be welded and the base metal with main pulse current, when the main pulse current is shifted from ON to OFF, a reverse pulse current having a polarity opposite to the polarity of the main pulse is supplied between the electrode and the base metal to improve the stiffness (directivity) of the arc by making the rising and falling edges of the pulses steeper. A rail-car and a nuclear power plant obtained by the method are also provided.Type: GrantFiled: July 9, 1998Date of Patent: May 1, 2001Assignee: Hitachi, Ltd.Inventors: Masayasu Nihei, Jin Onuki, Takao Funamoto, Izumi Sakurai, Akira Onuma
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Patent number: 5956231Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements beingType: GrantFiled: October 4, 1995Date of Patent: September 21, 1999Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Patent number: 5767577Abstract: A method of solder bonding suitable for a body having a large bonding surface area including the following steps of cleaning off the bonding surfaces in vacuum chamber by impinging accelerated particles such as argon ions through reverse spattering; then covering with an oxidation inhibiting thin silver film over the cleaned off bonding surfaces through spattering; further sandwiching a cleaned off solder foil between the bonding surfaces covered with the oxidation inhibiting thin sliver film; and heating the solder foil in vacuum upto the melting temperature thereof to complete the bonding, whereby defects in the solder bonding is reduced downto about 1/25 and life time of the solder bonding which is affected by thermal fatigue is prolonged twice in comparison with a conventional solder bonding method, thereby reliability of the solder bonding is greatly improved.Type: GrantFiled: December 6, 1995Date of Patent: June 16, 1998Assignee: Hitachi, Ltd.Inventors: Masayasu Nihei, Jin Onuki, Toshiaki Morita
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Patent number: 5539244Abstract: A first power semiconductor device with a semiconductor base to which an emitter wire electrode is connected through an emitter bonding pad and a gate wire electrode is connected through a gate bonding pad, wherein the gate bonding pad comprises a silicon oxide film, a silicon crystal layer and a gate wiring electrode made of aluminum containing silicon which are successively formed on the semiconductor base, and the gate wire electrode is connected to the gate wiring electrode. A second power semiconductor device wherein the emitter bonding pad is an emitter wiring electrode made of aluminum containing silicon which is directly formed on the semiconductor base, and the emitter wire electrode is bonded to the emitter wiring electrode.Type: GrantFiled: March 4, 1994Date of Patent: July 23, 1996Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Yasumichi Yasuda, Hiroyuki Ozawa, Jin Onuki
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Patent number: 5175608Abstract: A thin film forming method and apparatus, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is mounted between the target and the substrate and a high frequency current is made to flow therethrough to generate plasma. A negative base voltage smaller in absolute value than that during sputter may be applied to the substrate to make Ar ions flow into the substrate while it is subjected to reverse sputter. Thus, a film whose step coverage is 0.3 or more is possible. It becomes also possible to maintain a stable discharge and perform reverse sputter in a high vacuum region. The pressure of an Ar atmosphere may be lowered to 10.sup.-3 Torr or less. An aluminum wiring film whose peak value of x-ray diffraction strength at a (111) plane is 150 Kcps or more is possible.Type: GrantFiled: August 30, 1990Date of Patent: December 29, 1992Assignee: Hitachi, Ltd.Inventors: Masayasu Nihei, Jin Onuki, Yasushi Koubuchi, Kunio Miyazaki, Tatsuo Itagaki
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Patent number: 5153704Abstract: A resin encapsulated semiconductor device comprises a semiconductor element, a conductive base, a wire of aluminum connecting the element and the base, and a thermosetting resin encapsulating hermetically the component to protect the device from a mechanical stress and ambient atmosphere.Type: GrantFiled: January 3, 1992Date of Patent: October 6, 1992Assignee: Hitachi, Ltd.Inventors: Jin Onuki, Masateru Suwa, Masahiro Koizumi, Tomio Iizuka, Takeo Tamamura
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Patent number: 5051812Abstract: A semiconductor device having a high reliability wiring conductor structure applicable to DRAMs and SRAMs.The semiconductor device of the present invention is characterized by comprising a first wiring conductor film wherein a specific resistance is 5.about.15.mu..OMEGA.cm and an allowable current density is 1.times.10.sup.6 .about.1.times.10.sup.8 A/cm.sup.2 ; a second wiring conductor film having a laminated layer structure formed of a layer of high fusing point and low resistance material and a layer of an Al based alloy; and a plug composed of a high fusing point and low resistance material, electrically connecting to the first wiring conductor film and the second wiring conductor film. Thus, a semiconductor device showing almost no increase in electrical resistance in a wiring conductor film due to electromigration even after subjecting to a large current is provided.Type: GrantFiled: July 12, 1990Date of Patent: September 24, 1991Assignee: Hitachi, Ltd.Inventors: Jin Onuki, Masayasu Nihei, Yasushi Koubuchi, Motoo Suwa, Shinichi Fukada, Katsuhiko Shiota, Kunio Miyazaki, Tatsuo Itagaki, Jun Sugiura
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Patent number: 5019891Abstract: A semiconductor device and the method of fabricating the semiconductor device include a semiconductor substrate and a plurality of conductor films formed on the substrate. Each of the conductor films is made of aluminum alloy including at least one element selected from palladium and platinum and, more preferably, further including at least one element selected from lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chromium hafnium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobium, with a protective film which includes oxide of the selected one of palladium and platinum being formed on the side wall of the conductor film.Type: GrantFiled: January 12, 1989Date of Patent: May 28, 1991Assignee: Hitachi, Ltd.Inventors: Jin Onuki, Yasushi Koubuchi, Shinichi Fukada, Katuhiko Shiota, Kunio Miyazaki, Tatsuo Itagaki, Genji Taki
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Patent number: 4999096Abstract: A thin film forming method and apparatus is provided, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is mounted between the target and the substrate and a high frequency current is made to flow therethrough to generate plasma. A negative base voltage smaller in absolute value than that during sputter may be applied to the substrate to make a fraction of Ar ions to flow into the substrate while it is subjected to reverse sputter. Thus, a film whose step coverage is 0.3 or more is possible. It becomes also possible to hold stable discharge and reverse sputter at a high vacuum region. The pressure of an Ar atmosphere may be lowered to 10.sup.-3 Torr or less. A film whose peak value of x-ray diffraction strength in the (111) plane is 150 Xcps or more is possible.Type: GrantFiled: June 29, 1988Date of Patent: March 12, 1991Assignee: Hitachi, Ltd.Inventors: Masayasu Nihei, Jin Onuki, Yasushi Koubuchi, Kunio Miyazaki, Tatsuo Itagaki
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Patent number: 4976393Abstract: The present invention concerns a semiconductor device and a process for producing semiconductor device, as well as a wire bonding device used therefor.In accordance with the present invention, a ball formed at the top end of a bonding wire is sphericalized by electric discharge within a reducing gas atmosphere at a high temperature from 100.degree. C. to 200.degree. C. By using the ball of the bonding wire formed under such a condition to the bonding of the bonding pad of a semiconductor pellet, it is possible to conduct highly reliable ball bonding with excellent bondability and with no development of cracks or the like in the semiconductor pellet, as well as to obtain a highly reliable semiconductor device, that is, LSI or IC.Type: GrantFiled: December 17, 1987Date of Patent: December 11, 1990Assignee: Hitachi, Ltd.Inventors: Makoto Nakajima, Yoshio Ohashi, Toshio Chuma, Kazuo Hatori, Isao Araki, Masahiro Koizumi, Jin Onuki, Hitoshi Suzuki, Susumu Okikawa
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Patent number: 4965656Abstract: This invention provides a semiconductor device having an electrode conductor layer on a semiconductor substrate through the medium of a diffusion barrier layer, comprising the diffusion barrier layer formed of an amorphous material having a higher crystallization temperature than the heat treatment temperature for the semiconductor device. According to this invention, the reaction between the metal conductor and the semiconductor substrate and the diffusion of the conductor material into the semiconductor substrate can be prevented and resultantly a semiconductor device having a high thermal reliability can be obtained.Type: GrantFiled: February 21, 1989Date of Patent: October 23, 1990Assignee: Hitachi, Ltd.Inventors: Yasushi Koubuchi, Jin Onuki, Masahiro Koizumi
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Patent number: 4912544Abstract: A corrosion-resistant aluminum electronic material comprising an alloy containing aluminum as the principal component and, in addition, a small amount of a noble metal, the content of said noble metal being equal to or less than that at the eutectic point having the primary crystal of aluminum. As the noble metal, there is contained at least one metal selected from Pt, Pd, Rh, Ir, Os, Ru, Au and Ag. Said electronic material is used for ball-bonding wire and distributing film in a semiconductor device, and the like.Type: GrantFiled: August 10, 1983Date of Patent: March 27, 1990Assignee: Hitachi, Ltd.Inventors: Jin Onuki, Masateru Suwa, Masahiro Koizumi, Osamu Asai, Katsumi Suzuki, Ryo Hiraga
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Patent number: 4542398Abstract: A multi-emitter type semiconductor device, namely, a semiconductor device having an arrangement in which a majority of emitter regions are divided by a gate region and surrounded thereby. In the semiconductor device, a member adapted to apply an external control signal to a gate electrode takes the form of a closed-loop shape and the majority of emitter regions are arranged on both sides of the loop. This arrangement ensures that the individual emitter regions, even when the number of the emitter regions is increased to a great extent, can be applied with a uniform control signal, thereby preventing degradation of the turn-off characteristics.Type: GrantFiled: June 18, 1984Date of Patent: September 17, 1985Assignee: Hitachi, Ltd.Inventors: Tsutomu Yatsuo, Masayoshi Naito, Takahiro Nagano, Tomio Yasuda, Jin Onuki, Mitsuo Yanagi, Fumio Sato