Patents by Inventor Jin Onuki

Jin Onuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4500904
    Abstract: A solder joint between a semiconductor substrate and an electrode is disclosed in which that principal surface of the semiconductor substrate where an n-type semiconductor layer is exposed is bonded to the electrode with brazing solder, and the brazing solder includes aluminum solder provided on the side of the semiconductor substrate and copper solder provided on the side of the electrode. Since solid phase adhesion can be achieved between aluminum and copper even at temperatures below an eutectic temperature of 548.degree. C., the semiconductor substrate can be soldered to the electrode at the low temperatures.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: February 19, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Jin Onuki, Ko Soeno, Keiichi Morita, Hisakithi Onodera
  • Patent number: 4482912
    Abstract: Herein disclosed is a stacked or laminated structure which is rigidly integrated by sandwiching a metal layer between a first matrix-fiber composite layer prepared to have as a whole a thermal expansion coefficient and a second matrix-fiber layer prepared to have as a whole another thermal expansion coefficient different from that of the first matrix-fiber composite layer. The intervening metal layer acts as a buffer for the first and second matrix-fiber composite layers. The stacked structure according to the present invention can by used as the chip carrier of a semiconductor device, for example.
    Type: Grant
    Filed: February 2, 1982
    Date of Patent: November 13, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Akio Chiba, Seiki Shimizu, Keiichi Kuniya, Jin Onuki
  • Patent number: 4246693
    Abstract: There is provided a method of fabricating a semiconductor device wherein in a bonding surface of a silicon substrate of n-type conductivity are formed recesses having each a bonding surface of a higher order plane index than that of the bonding surface of the silicon substrate, and the substrate and electrodes and the like members are bonded together with an aluminum solder so as to decrease a forward voltage drop FVD. After forming the recesses but prior to the bonding with the aluminum solder, phosphor is diffused into a region ranging from the bonding surface to a depth of 20 microns, thereby further decreasing the forward voltage drop FVD. When cooling after the bonding, a temperature gradient is established so that temperature in the silicon substrate is higher than a temperature in the molten aluminum so that the forward voltage drop FVD can be decreased further.
    Type: Grant
    Filed: April 20, 1979
    Date of Patent: January 27, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Jin Onuki, Ko Soeno, Masateru Suwa, Hisakichi Onodera
  • Patent number: 4110783
    Abstract: A semi-conductor device comprising a silicon body having an exposed surface of N-type conductivity layer and a substrate bonded to the exposed surface by means of a layer of a new solder material, the solder material being an alloy consisting essentially of 2 to 12% by weight of at least one element of Group V of the periodic table, preferably antimony, and 0.01 to 5% by weight of at least one of rare earth elements, for example, Misch metal and aluminum being balance on the basis of total weight of the solder material. An increase in FVD of the device in which a conventional aluminum solder is used is prevented by the use of the new solder materials.
    Type: Grant
    Filed: February 7, 1977
    Date of Patent: August 29, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hisakichi Onodera, Masateru Suwa, Jin Onuki, Yoshiteru Shimizu