Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: A heater, a system, and a method for linearly changing the resistance of the phase change memory through a graded heater. The system may include a phase change memory. The phase change memory may include a dielectric. The phase change memory may also include a heater patterned on the dielectric, the heater including: an outside conductive heating layer that has a higher resistance than other layers of the heater, and an inside conductive heating layer that has a lower resistance than the outside conductive heating layer, where the outside conductive heating layer is at an outside area of the heater and the inside conductive heating layer is at an inside area of the heater. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

Abstract: A method for power saving and encryption during analysis of media captured by an information capture device using a partitioned neural network includes replicating, by an information capture device, an artificial neural network (ANN) from a computer server to the information capture device. The ANN on the computer server and a replicated ANN, both, include M layers. The method further includes, in response to captured data being input to be processed, partially processing, by the information capture device, the captured data by executing a first k layers using the replicated ANN, wherein only the k layers are selected to execute on the information capture device. The method further includes transmitting, by the information capture device, an output of the k-th layer to the computer server, which partially processes the captured data by executing the remainder of the M layers using the ANN and the output of the k-th layer.

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

Abstract: Described herein is a crossbar array that includes a cross-point synaptic device at each of a plurality of crosspoints. The cross-point synaptic device includes a weight storage element comprising a set of nanocrystal dots. Further, the cross-point synaptic device includes at least three terminals for interacting with the weight storage element, wherein a weight is stored in the weight storage element by sending a first electric pulse via a gate terminal from the at least three terminals, the first electric pulse causes the nanocrystal dots to store a corresponding charge, and the weight is erased from the weight storage element by sending a second electric pulse via the gate terminal, the second electric pulse having an opposite polarity of the first electric pulse.

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.