Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

Abstract: A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

Abstract: A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height. A channel region is interposed between opposing source/drain regions, and a gate stack is atop the semiconductor substrate. The gate stack includes an electrically conductive gate atop the channel region. The electrically conductive gate includes sidewalls extending between a base and an upper surface to define a gate height. A gate length of the electrically conductive gate continuously increases as the gate height increases from the base to the upper surface.

Abstract: A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height. A channel region is interposed between opposing source/drain regions, and a gate stack is atop the semiconductor substrate. The gate stack includes an electrically conductive gate atop the channel region. The electrically conductive gate includes sidewalls extending between a base and an upper surface to define a gate height. A gate length of the electrically conductive gate continuously increases as the gate height increases from the base to the upper surface.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

Abstract: A tunable resistance device and methods of forming the same include a magnetic fixed layer having a fixed magnetization, a magnetic free layer, and a non-magnetic conductive layer directly between the magnetic fixed layer and the magnetic free layer. The magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer are formed in a lattice of wires, with each wire in the lattice being formed from a stack of the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer.

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.