Patents by Inventor Jin Wen
Jin Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210098481Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang PU, Jin Wen DONG, Jun CHEN, Zhenyu LU, Qian TAO, Yushi HU, Zhao Hui TANG, Li Hong XIAO, Yu Ting ZHOU, Sizhe LI, Zhaosong LI
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Patent number: 10910390Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: July 26, 2018Date of Patent: February 2, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
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Patent number: 10892274Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.Type: GrantFiled: October 17, 2018Date of Patent: January 12, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi Hu, Qian Tao, Haohao Yang, Jin Wen Dong, Jun Chen, Zhenyu Lu
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Publication number: 20210005625Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
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Patent number: 10867678Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.Type: GrantFiled: September 21, 2018Date of Patent: December 15, 2020Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jun Chen, Jifeng Zhu, Zhenyu Lu, Yushi Hu, Jin Wen Dong, Lan Yao
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Patent number: 10847528Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.Type: GrantFiled: April 13, 2020Date of Patent: November 24, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
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Patent number: 10840125Abstract: The present invention relates to a memory structure and a method for forming the same. The memory structure includes a first substrate and an isolation structure. The first substrate includes a substrate layer and a storage layer. The substrate layer has a first surface and a second surface opposite to the first surface. The storage layer is disposed on the first surface of the substrate layer. The substrate layer has a doped well. The isolation structure penetrates through the substrate layer and is disposed at an edge of the doped well for isolating the doped well and the peripheral substrate layer. The memory structure can avoid current leakage between the doped well and the substrate layer so as to improve the performance.Type: GrantFiled: September 10, 2018Date of Patent: November 17, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jin Wen Dong, Jun Chen, Zhiliang Xia, Zi Qun Hua, Jifeng Zhu, He Chen
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Publication number: 20200243553Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
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Publication number: 20200211895Abstract: A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.Type: ApplicationFiled: February 27, 2019Publication date: July 2, 2020Inventors: Jian Xu, Liang Xiao, Jin Wen Dong, Meng Yan, Li Hong Xiao
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Patent number: 10692756Abstract: A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.Type: GrantFiled: February 27, 2019Date of Patent: June 23, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jian Xu, Liang Xiao, Jin Wen Dong, Meng Yan, Li Hong Xiao
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Patent number: 10644015Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.Type: GrantFiled: September 10, 2018Date of Patent: May 5, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
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Publication number: 20200035542Abstract: The present invention relates to a memory structure and a method for forming the same. The memory structure includes a first substrate and an isolation structure. The first substrate includes a substrate layer and a storage layer. The substrate layer has a first surface and a second surface opposite to the first surface. The storage layer is disposed on the first surface of the substrate layer. The substrate layer has a doped well. The isolation structure penetrates through the substrate layer and is disposed at an edge of the doped well for isolating the doped well and the peripheral substrate layer. The memory structure can avoid current leakage between the doped well and the substrate layer so as to improve the performance.Type: ApplicationFiled: September 10, 2018Publication date: January 30, 2020Inventors: Jin Wen Dong, Jun Chen, ZHILIANG XIA, Zi Qun Hua, JIFENG ZHU, He Chen
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Publication number: 20200027509Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.Type: ApplicationFiled: September 21, 2018Publication date: January 23, 2020Inventors: Jun Chen, Jifeng Zhu, Zhenyu Lu, Yushi Hu, Jin Wen Dong, Lan Yao
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Patent number: 10515975Abstract: A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.Type: GrantFiled: July 26, 2018Date of Patent: December 24, 2019Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qian Tao, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Jun Chen, Xiaowang Dai, Jin Lyu, Jifeng Zhu, Jin Wen Dong, Lan Yao
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Publication number: 20190378849Abstract: A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.Type: ApplicationFiled: July 26, 2018Publication date: December 12, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qian Tao, Yushi HU, Zhenyu Lu, Li Hong XIAO, Jun CHEN, Xiaowang DAI, Jin LYU, Jifeng ZHU, Jin Wen DONG, Lan YAO
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Patent number: 10497708Abstract: A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.Type: GrantFiled: September 12, 2018Date of Patent: December 3, 2019Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: He Chen, Jin Wen Dong, Jifeng Zhu, Zi Qun Hua, Liang Xiao, Yong Qing Wang
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Publication number: 20190326308Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: ApplicationFiled: July 26, 2018Publication date: October 24, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang PU, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
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Publication number: 20190139982Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.Type: ApplicationFiled: October 17, 2018Publication date: May 9, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi HU, Qian Tao, Haohao Yang, Jin Wen Dong, Jun Chen, Zhenyu Lu
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Publication number: 20190096901Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.Type: ApplicationFiled: September 10, 2018Publication date: March 28, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji Xia, Zhong ZHANG, Yan Ni LI
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Publication number: 20190074290Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, a method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.Type: ApplicationFiled: September 10, 2018Publication date: March 7, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong XIAO, Qian TAO, Yushi HU, Xiao Tian CHENG, Jian XU, Haohao YANG, Yue Qiang PU, Jin Wen DONG