Abstract: In a liquid crystal display device, the device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. The first substrate includes a pixel electrode, a thin film transistor connected to the pixel electrode, and also a hitch to connect both a lower and upper electrode of the pixel electrode. The second substrate includes a common electrode having a lower domain division part and an upper domain division part, in which each of domain division part is formed at the position corresponding to the lower and upper electrode of the pixel electrode, respectively. Through the electric field controller connected at both sides of the upper electrode of the pixel electrode, quality of display image can improve without a darkening area occurring at one part of the unit pixel.

Abstract: An array substrate includes a pixel electrode, a thin-film transistor (TFT) and a storage line. The pixel electrode has a first electrode portion, a second electrode portion and a connecting electrode portion to electrically connect the first and second electrode portions to each other. The second electrode portion is spaced apart from the first electrode portion by a predetermined distance in a first direction. The TFT is electrically connected to the pixel electrode to drive the pixel electrode. The storage line overlaps a portion of the pixel electrode and has an asymmetric connecting electrode closer to the second electrode portion than to the first electrode portion.

Abstract: This invention relates to the biosensor devices, their fabrication and use. The biosensor devices comprise a substrate supporting an array of microwells where each microwell can contain a biocompatible fluid and a membrane having a membrane protein of interest. In use the microwells can be addressable to detect and analyze a variety of analytes.

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a NMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: Nonvolatile memory capable of programming and erasure and method for fabricating the same, the method comprising the steps of (1) forming an oxide film on a first conduction type semiconductor substrate, (2) conducting an annealing in an NO or N2O ambient to convert the oxide film into a vertical lamination of a first silicon oxynitride region containing nitrogen and a second silicon oxynitride region containing relatively less nitrogen compared to the first silicon oxynitride region formed on the substrate, (3) patterning a gate electrode on the second oxynitride region, (4) forming second conduction type source, and drain impurity diffusion regions in surfaces of the substrate on both sides of the gate electrode, whereby facilitating a simple and easy fabrication process, a low programming voltage, a high performance, and a high device reliability.

Abstract: A separating region and a method of forming a separating region of a semiconductor device is provided that increases reliability of the device by isolating respective gate electrodes. The separating region and method prevent voids from being formed within a trench of the separating region. The method of forming the separating region includes forming patterns of first insulating layers on a semiconductor substrate by selectively etching the first insulating layers to have at least one opening disposed in a defined region of the semiconductor substrate, forming side walls of a second insulating layer on both lateral sides of the patterns of the first insulating layers, and etching the side walls of the second insulating layer and the exposed semiconductor substrate using the patterns of the first insulating layers as a mask to form trenches in the semiconductor substrate. Since a selectively ratio of the sidewalls and the semiconductor substrate is preferably 1:1, the trenches have a prescribed shape and depth.

Abstract: The present invention relates to the error control method in inter-multi-user multimedia communication. There are error detection, error reporting and error recovery functions in the conventional error control method which finds out and solve the error occurring at the time of data transmission between transmitter and receiver, however, these functions are an error control method occurring in end-to-end communication consisting of one transmitter and one receiver and are not appropriate to solving errors occurring concurrently and in a bundle between one or some transmitters and many receivers in many-to-many multiple points inter-multi-user communication such as multimedia communication. Therefore, the present invention uses the damping technique to minimize the number of error control packets of which all the receiver having sensed the error concurrently request the resend based on the NACK.

Abstract: A method of planarizing a multilayer semiconductor wiring structure includes the steps of forming a planarization layer on a substrate, forming a first conductive line pattern over the planarization layer, forming an insulation layer over the first conductive line pattern and the planarization layer, forming holes in the insulation layer to selectively expose portions of a top surface of the first conductive line pattern, forming a second conductive line pattern over the insulation layer, over portions of the first conductive line pattern, selectively in contact with the first conductive layer through the holes, and filling the holes, and forming a passivation layer over the second conductive line pattern, wherein conductive lines of the first conductive line pattern have a width of less than approximately 2 .mu.m.

Abstract: The method for forming an insulating film having a low dielectric constant, which is suitable for intermetal insulating film applications, by plasma enhanced chemical vapor deposition (PECVD) includes the step of supplying a first source gas containing fluorine and carbon to a dual-frequency, high density plasma reactor. The method also includes the step of supplying a second source gas containing silicon dioxide to the reactor. In this manner a fluorocarbon/silicon dioxide film is formed on a substrate in the reactor.

Abstract: A method for forming a device-isolating layer of a semiconductor device in which an APCVD oxide layer and an HDPCVD oxide layer are successively deposited to fill trenches. The method includes forming a thermal oxide layer on a semiconductor substrate including active regions and device-isolating regions, forming a nitride layer on the thermal oxide layer, selectively etching the nitride layer to be removed over the device-isolating regions and selectively etching the thermal oxide layer and the semiconductor substrate with the patterned nitride layer serving as a mask to form trenches. The method further includes forming another thermal oxide layer on the surface of the trenches, forming an APCVD oxide layer on the entire surface including the thermal oxide layer and the patterned nitride layer, forming and annealing an HDPCVD oxide layer on the entire surface of the APCVD oxide layer to fill the trenches. The HDPCVD oxide layer is then polished using a CMP process.

Abstract: A method for fabricating wiring in a semiconductor device in which a conductor line and a contact hole are formed by self-alignment, includes the steps of: forming an insulating layer on a substrate; forming an etch-step layer on the insulating layer; etching the etch-stop layer of a wiring region connected to a window and the insulating layer to a predetermined thickness; forming a mask layer on the etch-stop layer and the insulating layer; etching the mask layer to remove the mask layer at the central part of the window; and etching the insulating layer of the central part of the window so as to form a contact hole. By applying such a method, a highly improved reliability can be obtained, and a process thereof is simplified by a single photolithography. Also, the contact hole is formed by self-alignment in the lengthwise direction and in the vertical direction of the conductor line.

Abstract: A semiconductor memory cell structure includes a semiconductor substrate, a plurality of field insulating layers on the semiconductor substrate along a first direction at a first interval, a plurality of floating gate electrodes on the semiconductor substrate between the field insulating layers, the floating gate electrodes being aligned with the field insulating layers, a plurality of control electrodes over the floating gate electrodes and the field insulating layer at a second interval along a second direction, and a plurality of impurity areas on the semiconductor substrate at both sides of the floating gate electrodes along the first direction between the field insulating layers.