Patents by Inventor Jin Woo Han

Jin Woo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375921
    Abstract: A 3D device, the device including: a first level including logic circuits; and a second level including a plurality of memory cells, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the logic circuits include a programmable logic circuit.
    Type: Application
    Filed: August 8, 2021
    Publication date: December 2, 2021
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Publication number: 20210375829
    Abstract: A 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of arrays of memory cells, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2.
    Type: Application
    Filed: August 6, 2021
    Publication date: December 2, 2021
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20210366921
    Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than eight microns, where the second level includes a layer transferred and bonded level, where the bonded includes oxide to oxide bonds, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.
    Type: Application
    Filed: July 4, 2021
    Publication date: November 25, 2021
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Publication number: 20210358547
    Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
    Type: Application
    Filed: August 1, 2021
    Publication date: November 18, 2021
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Publication number: 20210336746
    Abstract: A method and apparatus for requesting uplink resources in a wireless communication system is provided. A user equipment determines whether a scheduling request for requesting uplink resources is triggered. If the scheduling request is triggered, the user equipment transmits a first set of frequency domain sequences and a second set of frequency domain sequences in a subframe.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Yeong Hyeon KWON, Seung Hee HAN, Hyun Woo LEE, Jae Hoon CHUNG, Jin Sam KWAK, Dong Cheol KIM, Min Seok NOH
  • Publication number: 20210335751
    Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.
    Type: Application
    Filed: July 11, 2021
    Publication date: October 28, 2021
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11158652
    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 26, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Patent number: 11158598
    Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.
    Type: Grant
    Filed: July 11, 2021
    Date of Patent: October 26, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20210325553
    Abstract: A MEMS nanotube based radiation sensor that is low cost, low power, compact, reliable and is applicable across many fields and a method for fabricating such a sensor are described. Each sensor may be connected to an array of similar but distinct sensors that leverage different materials and nanotube technology to detect radiation.
    Type: Application
    Filed: April 17, 2021
    Publication date: October 21, 2021
    Inventors: Zishan HAMEED, John GATS, Jin-Woo HAN, Meyya Meyyappan
  • Publication number: 20210329707
    Abstract: A base station transmits a random access response in response to a random access request (random access preamble) of a user equipment. The random access response includes information about a time when the random access request is transmitted and sequence number information of the random access request (random access preamble). The user equipment checks whether the received random access response is the response of the random access request transmitted by the user equipment, using the information about the time when the random access request is transmitted and the sequence number information included in the received random access response.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Inventors: Min Seok NOH, Yeong Hyeon KWON, Jin Sam KWAK, Dong Cheol KIM, Sung Ho MOON, Seung Hee HAN, Hyun Woo LEE, Dragan VUJCIC
  • Patent number: 11152386
    Abstract: A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors.
    Type: Grant
    Filed: February 3, 2018
    Date of Patent: October 19, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Publication number: 20210308685
    Abstract: One aspect of the present invention provides a nucleic acid amplification device. The nucleic acid amplification device includes a polymerase chain reaction (PCR) chip driving portion configured to allow a PCR chip to reciprocate between a first position and a second position; a plurality of first heating blocks disposed to be spaced apart with the first position as a center therebetween and to face each other; a plurality of second heating blocks disposed to be spaced apart with the second position as a center therebetween and to face each other; and a heating block driving portion configured to move the plurality of first heating blocks and the plurality of second heating blocks toward the PCR chip. Here, both surfaces of the PCR chip come into contact with the plurality of first heating blocks at the first position and the both surfaces sequentially come into contact with the plurality of second heating blocks at the second position so as to perform PCR.
    Type: Application
    Filed: July 31, 2019
    Publication date: October 7, 2021
    Inventors: Sung Woo KIM, Eun Sub KIM, Song Gyun JUNG, Jae Young BYUN, Jin Keun HAN
  • Publication number: 20210313345
    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 7, 2021
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Patent number: 11135572
    Abstract: The present invention relates to a method for preparing a supported catalyst comprising a crystalline Pd—Rh alloy, the method comprising the steps of: (i) producing an impregnated support by means of mixing an inorganic support, a Pd precursor solution and an Rh precursor solution; and (ii) thermally treating the impregnated support in a reducing gas atmosphere.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 5, 2021
    Assignee: HEESUNG CATALYSTS CORPORATION
    Inventors: Hyun-sik Han, Seung Chul Na, Jin-Woo Song, Narayana Rao Komateedi, Kwi-Yeon Lee
  • Patent number: 11134274
    Abstract: Provided is an apparatus and method for encoding/decoding a moving picture based on adaptive scanning. The moving picture apparatus and method can increase a compression rate based on adaptive scanning by performing intra prediction onto blocks of a predetermined size, and scanning coefficients acquired from Discrete Cosine Transform (DCT) of a residue signal and quantization differently according to the intra prediction mode. The moving picture encoding apparatus includes: a mode selector for selecting and outputting a prediction mode; a predictor for predicting pixel values of pixels to be encoded of an input video based on the prediction mode to thereby output a residue signal block; a transform/quantization unit for performing DCT onto the residue signal block and quantizing the transformed residue signal block; and an encoder for adaptively scanning and encoding the quantized residue signal block based on the prediction mode.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 28, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong-Il Seo, Wook-Joong Kim, Kyu-Heon Kim, Kyeong-Ok Kang, Jin-Woo Hong, Yung-Lyul Lee, Ki-Hun Han, Jae-Ho Hur, Dong-Gyu Sim, Seoung-Jun Oh
  • Publication number: 20210288010
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 16, 2021
    Inventors: Gyu Wan Han, Jin Seong Kim, Byong Woo Cho
  • Publication number: 20210288051
    Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 11121121
    Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits includes a first logic circuit and a second logic circuit, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of on-chip RF circuits, and where a portion of interconnections between the first logic circuit and the second logic circuit includes the plurality of on-chip RF circuits.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: September 14, 2021
    Assignee: MONOLITHIC 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11114464
    Abstract: A 3D device, the device including: a first level including logic circuits; a second level including a plurality of dynamic memory cells; and a third level including a plurality of non-volatile memory cells, where the first level is bonded to the second level, and where the device includes refresh circuits to refresh the dynamic memory cells.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: September 7, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 11114427
    Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: September 7, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han