Abstract: Disclosed is a display device including a display panel including a plurality of pixels and a voltage generator providing an anode initialization voltage to the pixels. The display panel is divided into a first display area operating at a first operating frequency and a second display area operating at a second operating frequency. While pixels, which correspond to the first display area, from among the plurality of pixels are driven, the anode initialization voltage has a first voltage level. While pixels in the second display area from among the plurality of pixels are driven, the anode initialization voltage has a second voltage level different from the first voltage level.

Abstract: A display device includes: a pixel electrically connected to a data line, a write scan line, an initialization scan line, a compensation scan line, a transmission control line, and an emission control line; a first driving circuit configured to provide a write scan signal to the write scan line and a second driving circuit configured to receive a plurality of clock signals, each of which has a time duration of one unit horizontal period and provide an initialization scan signal, a compensation scan signal, a transmission control signal, and an emission control signal to the initialization scan line, the compensation scan line, the transmission control line, and the emission control line, respectively. Each of the initialization scan signal and the compensation scan signal has an activation interval of one unit horizontal periods or more.

Abstract: A display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal. While an operating mode is a multi-frequency mode, the driving controller comparts the display panel into a first display area and a second display area. A hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven. The driving controller outputs the clock signal of a normal power mode during the first section and outputs the clock signal of a low-power mode during the second section.

Abstract: A display panel of a display device is divided into a first display region and a second display region. The second display region includes a boundary region adjacent to the first display region and a non-boundary region opposite to the first display region with respect to the boundary region. The driving controller outputs the voltage control signal, such that the first voltage in a first high voltage level and the second voltage in a first low voltage level are generated when the first display region is driven. The driving controller outputs the voltage control signal, such that the first voltage in a second high voltage level lower than the first high voltage level and the second voltage in a second low voltage level higher than the first low voltage level are generated, when the non-boundary region of the second display region is driven.

Abstract: Disclosed is a display device including a display panel including a plurality of pixels and a voltage generator providing an anode initialization voltage to the pixels. The display panel is divided into a first display area operating at a first operating frequency and a second display area operating at a second operating frequency. While pixels, which correspond to the first display area, from among the plurality of pixels are driven, the anode initialization voltage has a first voltage level. While pixels in the second display area from among the plurality of pixels are driven, the anode initialization voltage has a second voltage level different from the first voltage level.

Abstract: A display device includes: a pixel, a scan driver, an emission driver, and a data driver. The pixel includes: a light emitting element; a first transistor; a second transistor connected between a data line and a first node; a third transistor connected between a second node and a third node connected to a gate electrode of the first transistor; a fourth transistor connected between the second node and a third power line; a fifth transistor connected between the first node and a fourth node; a sixth transistor connected between a first power line and the first node and which is turned off in response to a first emission control signal; a storage capacitor connected between the third node and the fourth node; and a first capacitor connected between the first power line and the fourth node.

Abstract: A display device includes a display panel including a pixel which receives a luminance control voltage, a driving controller which receives an input image signal and a control signal and provides an output image signal to the display panel, and a voltage generator which generates the luminance control voltage in response to a voltage control signal from the driving controller. The driving controller determines a current operating frequency based on the control signal, and outputs the voltage control signal based on a difference value between the current operating frequency and a previous operating frequency and an operating time of the previous operating frequency when the current operating frequency is different from the previous operating frequency, where the luminance control voltage is changed from a first voltage level to a second voltage level based on the voltage control signal.

Abstract: A display device includes a light emitting element, a first transistor, and a second transistor connected between the first transistor and the light emitting element and including a gate electrode which receives an emission signal. One frame includes a first period a second period continuous with the first period. An emission off period of the emission signal has a first time duration during the first period, and the emission off period of the emission signal has a second time duration different from the first time duration during the second period.

Abstract: A display device includes: a display panel and a panel driver for driving the display panel during a plurality of driving frames whose frequencies are varied. Among the driving frames, a first driving frame having a first frequency includes a first write period, and a second driving frame having a second frequency lower than the first frequency includes a second write period and a variable blank period. The panel driver includes a data driver and a driving controller. Each of the first and second write periods includes N horizontal periods (N is an integer number equal to or greater than 1), each of the N horizontal periods has a first duration, and each of the first and second write periods has a second duration corresponding to N times of the first duration. The driving controller applies a training synchronizing signal to the data driver during the variable blank period.

Abstract: A display device includes a display panel including a pixel and a driving controller to drive the display panel. The driving controller generates a compensating signal, when a first driving frequency of a first frame is determined as being higher than a second driving frequency of a second frame by comparing a first cycle count value of the first frame with a second cycle count value of the second frame subsequent to the first frame.

Abstract: A display device includes: a pixel, a scan driver, an emission driver, and a data driver. The pixel includes: a light emitting element; a first transistor; a second transistor connected between a data line and a first node; a third transistor connected between a second node and a third node connected to a gate electrode of the first transistor; a fourth transistor connected between the second node and a third power line; a fifth transistor connected between the first node and a fourth node; a sixth transistor connected between a first power line and the first node and which is turned off in response to a first emission control signal; a storage capacitor connected between the third node and the fourth node; and a first capacitor connected between the first power line and the fourth node.

Abstract: A display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal. While an operating mode is a multi-frequency mode, the driving controller comparts the display panel into a first display area and a second display area. A hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven. The driving controller outputs the clock signal of a normal power mode during the first section and outputs the clock signal of a low-power mode during the second section.

Abstract: A display device includes: a data driver for supplying a data signal to each of a plurality of data lines; and a pixel unit including a plurality of sub-pixels. The pixel unit further includes one dummy data line disposed separate from a data line of a first column among the data lines. The data line of the first column is connected to sub-pixels disposed on odd-numbered pixel rows among sub-pixels disposed on a first pixel column, and is connected to sub-pixels disposed on even-numbered pixel rows among sub-pixels disposed on a third pixel column. The dummy data line is connected to sub-pixels disposed on the even-numbered pixel rows among the sub-pixels disposed on the first pixel column.

Abstract: A display device is disclosed that includes a pixel. The pixel includes a first transistor electrode connected between a second node and a third node and including a gate electrode connected to a first node. A first capacitor is formed between the first node and a fourth node. A second capacitor is formed between the fourth node and a first power line. A second transistor is connected between a data line and the fourth node. An eighth transistor is connected between the first power line and the second node. A ninth transistor is connected between the second node and a bias power line. A sixth transistor is connected between the third node and a fifth node. A light emitting element is electrically connected between the fifth node and a second power line. A gate electrode of the eighth transistor and a gate electrode of the sixth transistor are connected to different gate lines.

Abstract: A display device includes a display unit including a first pixel, a second pixel disposed adjacent to the first pixel in a first direction, a third pixel disposed adjacent to the first pixel in a second direction crossing the first direction, and a fourth pixel disposed adjacent to the third pixel in the first direction. Each of the first to fourth pixels includes a first sub-pixel and a second sub-pixel. The display device further includes a data driver that outputs a plurality of data voltages, a selective output unit that outputs the data voltages to the first to fourth pixels in a different order for each of a plurality of frames, and a scan driver that outputs a first scan signal to the first and second pixels and outputs a second scan signal, which is delayed from the first scan signal, to the third and fourth pixels.

Abstract: A display device includes a display panel including a plurality of pixels. At least one of the pixel includes a light emitting diode, a first transistor connected between a power line receiving a power source voltage and an anode of the light emitting diode, a second transistor connected between a data line and a first reference node, a first capacitor connected between the power line and the first reference node, a second capacitor connected between the first reference node and a second reference node, a third transistor connected between the first refence node and a reference voltage line receiving a reference voltage, a fourth transistor connected between an initialization voltage line receiving an initialization voltage and a drain of the first transistor, and a fifth transistor connected between the drain of the first transistor and the anode of the light emitting diode.

Abstract: A display device includes a display panel including a first pixel column in which first and third color pixels are alternately disposed, a second pixel column in which second color pixels are disposed, a third pixel column in which the third and first color pixels are alternately disposed, and a fourth pixel column in which the second color pixels are disposed. The display device further includes a scan driver applying a scan signal to scan lines, a data driver including a first source channel supplying a first color data signal and a second color data signal to a first data line, and a second source channel supplying the second color data signal and a third color data signal to a second data line, and a demultiplexer successively selecting the first and second sub-data lines during a period in which the scan signal is supplied to each scan line.

Abstract: Disclosed herein is a display device. The display device includes a plurality of data lines to supply data signals, a plurality of pixels each including a light-emitting element, a first transistor to control current flowing through the light-emitting element, and a second transistor connected between the first transistor and one of the plurality of data lines, and a conductive pattern disposed on and connected to the second transistor through a first contact hole. The data line is disposed on a layer different from that of the bridge pattern, and is connected to the bridge pattern through a second contact hole. The first contact hole and the second contact hole overlap each other, when viewed on a plane.

Abstract: A display device includes: a data driver for supplying a data signal to output lines; a demultiplexer connected to each of the output lines, the demultiplexer to supply the data signal supplied to each output line to a first data line and a second data line; first pixels disposed in a (2j?1)-th column and a (2k?1)-th row, the first pixels being connected to the first data line, wherein j and k are positive integers; second pixels disposed in the (2j?1)-th column and a (2k)-th row, the second pixels being connected to the second data line; third pixels disposed in a (2j)-th column and the (2k?1)-th row, the third pixels being connected to the first data line; and fourth pixels disposed in the (2j)-th column and the (2k)-th row, the fourth pixels being connected to the second data line.

Abstract: A display device includes a display panel including a first pixel connected to a first initialization scan line and a first compensation scan line and a second pixel connected to a second initialization scan line and a second compensation scan line, a scan driving circuit which provides a first initialization scan signal to the first initialization scan line and the second initialization scan line in common and provides a first compensation scan signal and a second compensation scan signal to the first compensation scan line and the second compensation scan line, and a driving controller which controls the scan driving circuit. A delay time from a time point at which the first initialization scan signal transitions from an active level to an inactive level to a time point at which the first compensation scan signal transitions from the inactive level to the active level is less than one horizontal period.