Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: Aspects of the disclosure provide a circuit that includes a decoder, an error checking module, and a controller. The decoder is configured to receive codewords, and decode the codewords based on an error correcting code. The error checking module is configured to error-check sectors using an error detecting code in the sectors. Each sector is formed of a plurality of decoded codewords. The controller is configured to store in a memory, when the error checking fails for at least one sector, the decoded codewords and corresponding flags indicative of pass or fail of the decoding of the codewords.

Abstract: A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Abstract: The invention provides a unique catalyst system without the need for carbon. Metal nanoparticles were grown onto conductive, two-dimensional material of TiSi2 nanonet by atomic layer deposition. The growth exhibited a unique selectivity with the elemental metal deposited only on defined surfaces of the nanonets in nanoscale without mask or patterning.

Abstract: A differential phase detector for an optical storage system is set forth. The differential phase detector includes a photodetector circuit arranged to detect light deviations associated with radial errors in the optical storage system. A non-linear equalizer is in communication with the photodetector circuit. The output of the non-linear equalizer is in communication with signal processing circuitry. The signal processing circuitry uses the equalized signals to generate one or more radial error signals.

Abstract: Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.

Abstract: New and useful methods and systems for providing improved performance of a Viterbi device are disclosed. For example, in an embodiment a Viterbi device includes metric circuitry configured to determine branch metrics using at least one of a variance signal based on both received data and detected data of the Viterbi device and a priori probabilities of available state transitions within a trellis of the Viterbi device.

Abstract: A decoder including a decode module, a matrix module, and a marking module. The decode module receives data and performs a first decoding iteration to decode the data. The first decoding iteration includes generating a first matrix having a first byte. The matrix module generates a second matrix based on the first matrix. The second matrix includes the first and second bytes. The second byte is adjacent and sequentially prior or subsequent to the first byte. The marking module: determines whether the first byte has been correctly decoded; based on determining whether the first byte has been correctly decoded, determines a status of the second byte; and based on the status of the second byte, marks the first byte as an erasure. The decode module, based on the second byte being marked as an erasure, corrects the second byte during the second decoding iteration.

Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected.

Abstract: Devices, methods, and other embodiments associated with adjusting a defect threshold are described. In one embodiment, an apparatus includes defect detection logic and threshold adjustment logic. The defect detection logic determines, by using a defect threshold, if a read channel has read data from a defective portion of an optical disc. The threshold adjustment logic adjusts the defect threshold based, at least in part, on a gain value of a gain loop associated with the read channel.

Abstract: A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.

Abstract: A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Abstract: Aspects of the disclosure provide a sync mark detector. The sync mark detector includes a first unit configured to decay over time a value indicating a length of a bit format, a second unit configured to compare the decayed value with a detected length of the bit format to determine a new length, and a third unit configured to detect a sync mark based on the detected length and the new length.

Abstract: A differential phase detector for an optical storage system is set forth. The differential phase detector includes a photodetector circuit arranged to detect light deviations associated with radial errors in the optical storage system. A non-linear equalizer is in communication with the photodetector circuit. The output of the non-linear equalizer is in communication with signal processing circuitry. The signal processing circuitry uses the equalized signals to generate one or more radial error signals.

Abstract: Described herein are pyrrolo[2,3-d]pyrimidine compounds, their use as Janus Kinase (JAK) inhibitors, pharmaceutical compositions containing these compounds, and methods for their preparation.

Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: Asymmetry and offset compensation for a data signal may be performed by a compensation circuit as disclosed. A circuit can be configured to generate a compensated data signal from a data signal, and can include: an input node inputting the data signal, an offset coefficient feedback loop configured to calculate an offset coefficient based on the data signal, a scaling unit configured to scale the offset coefficient by a first predetermined value (the scaled offset coefficient representing an estimate of an asymmetry coefficient), an asymmetry coefficient feedback loop configured to calculate the asymmetry coefficient based on the data signal and an initial value, a signal selection unit that causes the circuit to calculate the compensated data signal using the asymmetry coefficient, and an output node that outputs the compensated data signal.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: An aspect of the disclosure provides a signal processing circuit that decouples a timing loop and an equalizer adaptation loop. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a detector, and a timing module. The ADC is configured to receive an analog signal, sample the analog signal based on a sampling clock signal, and convert the sampled analog signal into a digital signal. The equalizer is configured to equalize the digital signal. The detector is configured to detect a bit stream from the equalized digital signal. The timing module is configured to detect a timing error based on the digital signal before being equalized, and to adjust the sampling clock signal based on the timing error.