Abstract: An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter configured to sense a voltage level of the floating plate; a first transfer gate connected with the tunneling plate and configured to transfer an operating voltage selectively applied from first and second bit lines to the tunneling plate; a protection circuit connected with the inverter and configured to float the inverter at non-read or write/erase operations of an adjacent EEPROM cell; and a second transfer gate configured to transfer an output voltage of the inverter. This configuration is enable to use all the same gate oxide (i.e. 26 ?) and ultra low operation voltages (i.e. ±2V) in EEPROM cell.

Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.

Abstract: An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter configured to sense a voltage level of the floating plate; a first transfer gate connected with the tunneling plate and configured to transfer an operating voltage selectively applied from first and second bit lines to the tunneling plate; a protection circuit connected with the inverter and configured to float the inverter at non-read or write/erase operations of an adjacent EEPROM cell; and a second transfer gate configured to transfer an output voltage of the inverter. This configuration is enable to use all the same gate oxide (i.e. 26 ?) and ultra low operation voltages (i.e. ±2V) in EEPROM cell.

Abstract: An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM cell in response to the control signals; and a word line control circuit configured to control a sense gate line in response to the control signals at a sense operation and to apply a positive voltage and a negative voltage to a word line.

Abstract: A terminal and an operation control method thereof are disclosed. A terminal performs an authentication procedure upon receiving a tag device's information from the tag device. If the tag device is identified as a registered tag device in the authentication procedure, initial data corresponding to a function to control the terminal even in a power-saving mode or a lock mode is received from the tag device, and the function corresponding to the initial data is performed.

Abstract: An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated.

Abstract: An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated.

Abstract: In an EEPROM cell, as a storage capacitor is added between a control plate and a tunneling plate, after the storage capacitor is charged for a time that is relatively smaller than a time necessary for writing or erasing data of the EEPROM cell, the EEPROM cell that can perform operation of writing or erasing data of the EEPROM cell using a charge voltage that is stored at the storage capacitor is provided. Therefore, operation of writing or erasing data of the EEPROM cell within a short time using the EEPROM cell can be performed, and thus entire productivity of the EEPROM can be improved.

Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.

Abstract: An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.

Abstract: Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5×1015/cm3 to 2×1016/cm3; and a transfer transistor that is connected to the photo detector and is formed of a vertical type trench gate of which the equivalent oxide thickness is 120 ? or more.

Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes ar

Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.

Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.

Abstract: Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

Abstract: Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5×1015/cm3 to 2×1016/cm3; and a transfer transistor that is connected to the photo detector and is formed of a vertical type trench gate of which the equivalent oxide thickness is 120 ? or more.

Abstract: An inorganic electroluminescent device includes: patterned metal electrodes periodically disposed at pre-set intervals; and a phosphor layer positioned on the patterned metal electrodes, wherein as a first voltage and a second voltage are alternately applied to the patterned metal electrodes according to the order of their disposition, light emitted from the phosphor layer is discharged to the spaces between the patterned metal electrodes.

Abstract: Provided is an image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by SiGe BiCMOS technology. In the image sensor, a PD employs a floating-base-type SiGe HBT. A floating base of the SiGe HBT produces a positive voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. The SiGe HBT can sense an optical current signal and also amplify the optical current signal. The image sensor requires only three transistors in a pixel so that the degree of integration can increase. The image sensor has an improved sensitivity of signals in the short wavelength region and a sensing signal has excellent linearity such that both a sensing mechanism and control circuit are very simple.

Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Abstract: Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly doped p-type SiGeC epitaxial layer or a polysilicon layer deposited on a top surface of the p-type well over the internal n-type region. The image sensor includes: a photo diode including an internal n-type region and a surface p-type region; a transfer transistor for transmitting photo-charges generated in the photo diode to a floating diffusion node; and a driving transistor for amplifying a variation in an electric potential of the floating diffusion node due to the photo-charges. The image sensor further includes a floating metal layer for functioning as the floating diffusion node and applying an electric potential from a drain of the transfer transistor to a gate of the driving transistor.