Abstract: The present invention is a wafer carrier with adjustable aligning devices, which is suitable for a deposition machine. The wafer carrier comprises a tray and a plurality of adjustable aligning devices. The adjustable alignment devices are located around the tray, and include a base and an alignment pin. The adjustable alignment devices are configured to align a clamp ring of the deposition machine. The alignment pin is connected to the tray through the base, wherein the alignment pins and the bases are able to move relative to the tray to adjust the position of the alignment pins. Further, an alignment fixture can be placed on the wafer carrier to position the adjustable alignment devices around the tray, and adjust the alignment pins to preset positions, which is beneficial to improve the accuracy of alignment of the clamp ring.

Abstract: The invention is directed to an embedded hydrogel contact lens, which comprises an insert sandwiched between two layers of hydrogel materials and can be produced according to a cast molding method including the procedures involving two females halves (FC1 and FC2) and two male halves (BC1 and BC2) and three consequential molding steps involving three molding assemblies: the 1st one formed between FC1 and BC1 for molding an insert; the 2nd one formed between FC1 and BC2 for molding a lens precursor having the molded insert embedded in a layer of a hydrogel material in a way that the front surface of the molded insert merges with the convex surface of the lens precursor; and the 3rd one formed between FC2 and BC2 for molding an embedded hydrogel contact of the invention.

Abstract: A network management system includes a memory and processing circuitry in communication with the memory. The processing circuitry is configured to obtain connection event data. The connection event data indicates a plurality of disconnection events. The processing circuitry is also configured to generate, from the connection event data, aggregate data according to a plurality of network scope levels and detect, based on the aggregate data, one or more network anomalies. Additionally, the processing circuit is configured to determine, based on the aggregate data, whether a root cause of the one or more network anomalies is associated with each network scope level of the plurality of network scope levels and output an indication of the determined network scope level associated with the root cause or performing a remedial action to address the root cause at the determined network scope level.

Abstract: A semiconductor package includes a package substrate, an interposer disposed on the package substrate, the interposer including a first surface and a second surface opposite to the first surface, a first semiconductor device mounted on the second surface of the interposer, a second semiconductor device disposed on the second surface and spaced apart from the first semiconductor device in a first horizontal direction that is parallel to the second surface, and a warpage prevention structure disposed on the first surface of the interposer at a position on the first surface that corresponds to a position between the first semiconductor device and the second semiconductor device on the second surface of the interposer and that vertically overlaps the first semiconductor device and the second semiconductor device.

Abstract: A semiconductor package includes: a first wiring structure including at least one first wiring pattern and a first insulating layer including the first wiring pattern therein; a second wiring structure including at least one second wiring pattern and a second insulating layer including the second wiring pattern therein; a semiconductor chip between the first wiring structure and the second wiring structure; a molding layer between the first wiring structure and the second wiring structure, the molding layer comprising the semiconductor chip therein; and a conductive post penetrating the molding layer and configured to electrically connect the first wiring structure to the second wiring structure, wherein the conductive post includes: a body extended through the molding layer in a vertical direction; and a bonding surface on a side surface of the body and having a greater roughness than an upper surface and a lower surface of the conductive post.

Abstract: A semiconductor chip includes a semiconductor substrate, a bonding layer above an upper surface of the semiconductor substrate, the bonding layer including a bonding pad and a bonding insulating layer surrounding at least a portion of a side surface of the bonding pad, and a circuit layer between the semiconductor substrate and the bonding layer, the circuit layer including a circuit insulating layer and an electric line in the circuit insulating layer, where a horizontal width of the circuit layer is less than a horizontal width of the semiconductor substrate, and a sidewall of the semiconductor substrate is spaced apart from a sidewall of the circuit layer in a horizontal direction.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Abstract: A semiconductor package includes: a first redistribution substrate; a first semiconductor chip on the first redistribution substrate, the first semiconductor chip comprising a semiconductor substrate and a plurality of first thermal vias penetrating through the semiconductor substrate in a first direction; a second semiconductor chip disposed on a center portion of the first semiconductor chip; and a plurality of second thermal vias arranged on a peripheral portion of the first semiconductor chip and arranged on an outer portion of the second semiconductor chip, wherein the plurality of second thermal vias are connected to the plurality of first thermal vias, respectively.

Abstract: A nucleic acid extraction composition, reagents and kits containing the same and uses thereof. Provided is a nucleic acid extraction and purification reagent free of volatile organic solvents, which prevents the damage of volatile organic solvents to people and greatly improves the timeliness of nucleic acid extraction and purification, making the operation extremely simple, and the nucleic acid can be obtained within 10 minutes. The obtained nucleic acid may be used for biological reactions such as PCR, NASBA, LAMP and RPA. Moreover, the reagents of the present disclosure may be used to extract nucleic acids of cells, bacteria, fungi, DNA viruses and RNA viruses from various samples such as blood, throat swab preserving fluid, saliva, urine, sputum, excrement and the like, and very suitable for clinical and scientific research uses.

Abstract: Techniques are described by which a network management system (NMS) is configured to provide identification of root cause failure through the detection of network scope failures. For example, the NMS comprises one or more processors; and a memory comprising instructions that when executed by the one or more processors cause the one or more processors to: generate a hierarchical attribution graph comprising attributes representing different network scopes at different hierarchical levels; receive network event data, wherein the network event data is indicative of operational behavior of the network, including one or more of successful events or one or more failure events associated with one or more client devices; and apply a machine learning model to the network event data and to a particular network scope in the hierarchical attribution graph to detect whether the particular network scope has failure.

Abstract: Provided are a D-amino acid oxidase and use thereof in the preparation of L-phosphinothricin or an intermediate thereof. Provided is a D-amino acid oxidase having an amino acid sequence comprising an amino acid residue difference as compared to SEQ ID NO: 1, the amino acid residue difference being selected from one or a plurality of: K29G/H/I/N/Q/W/Y/C/L; V42C/D/E/H/Y; E195N/Y/Q; C234L; and V326W. The activity and/or thermal stability of the D-amino acid oxidase is not lower than that of a D-amino acid oxidase having an amino acid sequence as set forth in SEQ ID NO: 1. Provided is a D-amino acid oxidase with higher thermal stability. The operating temperature range of the enzyme is expanded while the activity of the enzyme is improved. The enzyme can have a prolonged service life when used at a relatively low temperature, and can have an improved catalytic efficiency when used at a relatively high temperature.

Abstract: A semiconductor package includes a substrate including: a substrate comprising a through-hole; a first semiconductor chip in the through-hole; an adhesive layer on a side surface of the first semiconductor chip in the through-hole; a first redistribution structure on an upper surface of the substrate and bonded and connected to the substrate; a second redistribution structure on a lower surface of the substrate and bonded and connected to the substrate; a second semiconductor chip on the first redistribution structure; and a through-via spaced apart from the first semiconductor chip in a horizontal direction and passing through the substrate in a vertical direction.

Abstract: A semiconductor package includes a first semiconductor chip including a plurality of upper pads, a non-conductive support layer on a top surface of the first semiconductor chip and including a plurality of openings, a second semiconductor chip on the first semiconductor chip and including a plurality of lower pads, a plurality of chip connecting terminals extending between the plurality of upper pads and the plurality of lower pads, and an insulation adhesive layer between the first semiconductor chip and the second semiconductor chip and at least partially covering the plurality of chip connecting terminals and the non-conductive support layer. A top surface of the non-conductive support layer is disposed closer to a bottom surface of the second semiconductor chip than top surfaces of the plurality of upper pads are disposed to the bottom surface of the second semiconductor chip.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for providing a secure development environment for developing computer models by utilizing an exploration environment in conjunction with a production environment. In particular, the disclosed systems provide a method for a client account to develop machine learning models securely and efficiently (e.g., access, generate, train, and activate) by utilizing a scalable exploration environment isolated from a production environment. Further, the disclosed systems can provide a system for the client account to utilize to convert the exploration model to a production model and activate the production model within the production environment. In this way, the disclosed systems provide a separation between the exploration environment and the production environment when testing models and thus constrain the impact of testing models to the production environment.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: Provided is a semiconductor package and method of manufacturing same, the semiconductor package including: a first semiconductor chip; a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips; a third semiconductor chip on the chip stacked structure; an adhesive layer between the chip stacked structure and the third semiconductor chip; and a first pad pattern on a lower surface of the third semiconductor chip, wherein the adhesive layer surrounds the first pad pattern and the adhesive layer is between the first pad pattern and the chip stacked structure.

Abstract: An electronic device includes a first screen and a second screen. A high-power sensor of the electronic device is in a disabled state, and a low-power sensor of the electronic device is in an enabled state. The electronic device includes a foldable device. Based on this, after the electronic device receives a screen-on trigger signal from the low-power sensor or a processor of the electronic device, the electronic device determines a to-be-lit-up first target screen based on the screen-on trigger signal, and then controls the first target screen to be lit up.

Abstract: Provided is a semiconductor package, including a first redistribution structure, a first chip on the first redistribution structure, a molding member on the first redistribution structure and surrounding the first chip, a conductive pillar penetrating through the molding member in a first direction, a second redistribution structure on a second surface of the molding member, a second chip on the second redistribution structure, and a heat dissipation chip at least partially overlapping the first chip in the vertical direction, wherein the second redistribution structure at least partially overlaps the heat dissipation chip in a second direction intersecting the first direction.

Abstract: A semiconductor package includes a lower redistribution structure, an internal semiconductor chip on the lower redistribution structure and including first connection pads on a lower surface of the internal semiconductor chip, conductive posts connected to the lower redistribution structure, an encapsulant surrounding a side surface of each of the conductive posts, surrounding a side surface of the internal semiconductor chip, and covering an upper surface of the internal semiconductor chip, upper trace pads on the encapsulant and respectively connected to ends of the conductive posts, an external semiconductor device on the encapsulant, the external semiconductor device including second connection pads on a lower surface of the external semiconductor device and respectively connected to the upper trace pads, and a heat dissipation structure on the encapsulant and laterally spaced apart from the external semiconductor device.