Abstract: Provided are a D-amino acid oxidase and use thereof in the preparation of L-phosphinothricin or an intermediate thereof. Provided is a D-amino acid oxidase having an amino acid sequence comprising an amino acid residue difference as compared to SEQ ID NO: 1, the amino acid residue difference being selected from one or a plurality of: K29G/H/I/N/Q/W/Y/C/L; V42C/D/E/H/Y; E195N/Y/Q; C234L; and V326W. The activity and/or thermal stability of the D-amino acid oxidase is not lower than that of a D-amino acid oxidase having an amino acid sequence as set forth in SEQ ID NO: 1. Provided is a D-amino acid oxidase with higher thermal stability. The operating temperature range of the enzyme is expanded while the activity of the enzyme is improved. The enzyme can have a prolonged service life when used at a relatively low temperature, and can have an improved catalytic efficiency when used at a relatively high temperature.

Abstract: A semiconductor package includes a first semiconductor chip including a plurality of upper pads, a non-conductive support layer on a top surface of the first semiconductor chip and including a plurality of openings, a second semiconductor chip on the first semiconductor chip and including a plurality of lower pads, a plurality of chip connecting terminals extending between the plurality of upper pads and the plurality of lower pads, and an insulation adhesive layer between the first semiconductor chip and the second semiconductor chip and at least partially covering the plurality of chip connecting terminals and the non-conductive support layer. A top surface of the non-conductive support layer is disposed closer to a bottom surface of the second semiconductor chip than top surfaces of the plurality of upper pads are disposed to the bottom surface of the second semiconductor chip.

Abstract: A semiconductor package includes a substrate including: a substrate comprising a through-hole; a first semiconductor chip in the through-hole; an adhesive layer on a side surface of the first semiconductor chip in the through-hole; a first redistribution structure on an upper surface of the substrate and bonded and connected to the substrate; a second redistribution structure on a lower surface of the substrate and bonded and connected to the substrate; a second semiconductor chip on the first redistribution structure; and a through-via spaced apart from the first semiconductor chip in a horizontal direction and passing through the substrate in a vertical direction.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for providing a secure development environment for developing computer models by utilizing an exploration environment in conjunction with a production environment. In particular, the disclosed systems provide a method for a client account to develop machine learning models securely and efficiently (e.g., access, generate, train, and activate) by utilizing a scalable exploration environment isolated from a production environment. Further, the disclosed systems can provide a system for the client account to utilize to convert the exploration model to a production model and activate the production model within the production environment. In this way, the disclosed systems provide a separation between the exploration environment and the production environment when testing models and thus constrain the impact of testing models to the production environment.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: Provided is a semiconductor package and method of manufacturing same, the semiconductor package including: a first semiconductor chip; a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips; a third semiconductor chip on the chip stacked structure; an adhesive layer between the chip stacked structure and the third semiconductor chip; and a first pad pattern on a lower surface of the third semiconductor chip, wherein the adhesive layer surrounds the first pad pattern and the adhesive layer is between the first pad pattern and the chip stacked structure.

Abstract: An electronic device includes a first screen and a second screen. A high-power sensor of the electronic device is in a disabled state, and a low-power sensor of the electronic device is in an enabled state. The electronic device includes a foldable device. Based on this, after the electronic device receives a screen-on trigger signal from the low-power sensor or a processor of the electronic device, the electronic device determines a to-be-lit-up first target screen based on the screen-on trigger signal, and then controls the first target screen to be lit up.

Abstract: Provided is a semiconductor package, including a first redistribution structure, a first chip on the first redistribution structure, a molding member on the first redistribution structure and surrounding the first chip, a conductive pillar penetrating through the molding member in a first direction, a second redistribution structure on a second surface of the molding member, a second chip on the second redistribution structure, and a heat dissipation chip at least partially overlapping the first chip in the vertical direction, wherein the second redistribution structure at least partially overlaps the heat dissipation chip in a second direction intersecting the first direction.

Abstract: A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

Abstract: A semiconductor package includes a lower redistribution structure, an internal semiconductor chip on the lower redistribution structure and including first connection pads on a lower surface of the internal semiconductor chip, conductive posts connected to the lower redistribution structure, an encapsulant surrounding a side surface of each of the conductive posts, surrounding a side surface of the internal semiconductor chip, and covering an upper surface of the internal semiconductor chip, upper trace pads on the encapsulant and respectively connected to ends of the conductive posts, an external semiconductor device on the encapsulant, the external semiconductor device including second connection pads on a lower surface of the external semiconductor device and respectively connected to the upper trace pads, and a heat dissipation structure on the encapsulant and laterally spaced apart from the external semiconductor device.

Abstract: A semiconductor package manufacturing apparatus is provided and includes a bonding head including at least one vacuum hole, and at least one adsorption trench in a lower surface of the bonding head and connected to the at least one vacuum hole. A lower part of the bonding head includes at least one first portion, and a second portion spaced apart from the at least one first portion and surrounding the at least one first portion in a plan view. The at least one adsorption trench is defined by and between the at least one first portion and the second portion, and at least a portion of an inner surface of the at least one adsorption trench and at least a portion of an outer surface of the at least one adsorption trench are curved in the plan view.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, the first semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips including a second semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of conductive patterns on the active surface of each second semiconductor substrate of the plurality of second semiconductor chips, and a plurality of bonding pads on the inactive surface of the first semiconductor substrate and on the inactive surface of each second semiconductor substrate of the plurality of second semiconductor chips, where the plurality of bonding pads are respectively connected to the plurality of conductive patterns.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip hybrid-bonded to the first semiconductor chip. The first semiconductor chip includes first main pads, which are apart from each other, and a first bonding insulation layer extending around the first main pads. Each of the first main pads includes first sub main pads apart from each other. The second semiconductor chip includes second main pads, which are spaced apart from each other, and a second bonding insulation layer extending around the second main pads. The second main pads are aligned with the first main pads. Each of the second main pads includes second sub main pads spaced apart from each other. Each of the second sub main pads is bonded to a respective one of the first sub main pads. The second bonding insulation layer is bonded to the first bonding insulation layer.

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Abstract: A method of wafer bonding includes the following operations. A first surface of the handle wafer, a second surface of the device wafer, or a combination thereof, is coated with water. When the first surface of the handle wafer is coated with water, the handle wafer is rotated at a first rotational speed. When the second surface of the device wafer is coated with water, the device wafer is rotated at a second rotational speed. When the first surface of the handle wafer and the second surface of the device wafer are coated with water, the handle wafer is rotated at a third rotational speed, and the device wafer is rotated at a fourth rotational speed. The first surface of the handle wafer and the second surface of the device wafer are bonded.

Abstract: The present invention belongs to animal experiments field, disclosed a single factor modeling-constraint method and device for mice chronic fatigue syndrome, the modeling-constraint method is specifically using mineral water bottle to restraint mice; the mineral water bottle is divided into upper, middle and lower parts; the body of mineral water bottle is uniformly drilled for mice to breathe; the inner of the mineral water bottle is blocked by a cardboard to reduce the move space of mice; cover the mice through the divided bottle; one end of the opening is tightly attach to the wall, the other end is tightly attach to the mice feeding box, and keeping 30 minutes to restraint. The present invention utilizes mineral water bottle to make three simple restraint tube, not only saves the costs of experiment, but also turns waste into treasure, which is a simple operation, and increases the possibility of the experiment.

Abstract: The present disclosure provides a thin-film-deposition equipment, which includes a main body, a carrier and a shielding device, wherein a portion of the shielding device and the carrier are disposed within the main body. The main body includes a reaction chamber, and two sensor areas connected to the reaction chamber, wherein the sensor areas are smaller than the reaction chamber. The shielding device includes a first-shield member, a second-shield member and a driver. The driver interconnects the first-shield member and the second-shield member, for driving the first-shield member and the second-shield member to move in opposite directions. During a deposition process, the two shield members are separate from each other into an open state, and respectively enter the two sensor areas. During a cleaning process, the driver swings the shield members toward each other into a shielding state for covering the carrier.