Patents by Inventor Jing Feng

Jing Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11495178
    Abstract: A pixel circuit includes a data writing sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The data writing sub-circuit is connected to the driving sub-circuit, and is configured to write a data voltage signal into the driving sub-circuit and compensate it, in response to a first gate signal and a second gate signal. The light-emitting control sub-circuit is connected to the driving sub-circuit, and is configured to close a line between a first power supply voltage terminal and a second power supply voltage terminal, in response to a first enable signal and a second enable signal. The driving sub-circuit is configured to provide a driving current to a light-emitting device through the closed line according to the written data voltage signal. Phases of the first enable signal and the first gate signal are opposite, and phases of the second enable signal and the second gate signal are opposite.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 8, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Zhichong Wang, Fuqiang Li, Peng Liu, Xinglong Luan, Jing Feng
  • Publication number: 20220344712
    Abstract: Monomers for preparing a polymer electrolyte precursor composition capable to form an in-situ polymerized polymer electrolyte, which comprise, consist essentially of, or consist of A1) a first monomer and A2) a second monomer. A polymer electrolyte precursor raw material composition, a polymer electrolyte precursor composition capable to form a polymer electrolyte comprising the monomers, a polymer electrolyte and an electrochemical device are also provided.
    Type: Application
    Filed: June 6, 2019
    Publication date: October 27, 2022
    Inventors: Shasha Su, Jinhua Jiang, Jing Feng, Hongping Li, Huichao Lu, Zhixin Xu, Jun Yang
  • Publication number: 20220336519
    Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.
    Type: Application
    Filed: May 17, 2021
    Publication date: October 20, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Zhaoyao Zhan, Jing Feng, Qianwei Ding, Xiaohong Jiang, Ching-Hwa Tey
  • Publication number: 20220276230
    Abstract: A test stick, a testing method and application. A top cover and a bottom cover are engaged by means of positioning holes (D01) and positioning posts (G01) so as to fix a test strip; clamp slot structures (D02, D06) and a bulge stage (D04) are provided inside the bottom cover; each of the clamp slot structures (D02, D06) is internally provided with a support bulge (D03), with the height of the support bulge (D03) being less than or equal to the height of the bulge stage (D04); the top cover is provided with fixing plates (G02, G03, G04, G06), a reaction window (G05), a sample loading hole (A) and a testing liquid hole (B); and after the top cover and the bottom cover are engaged by means of the positioning holes (D01) and the positioning posts (G01), under the pressing of the fixing plates (G02, G03, G04, G06) and the testing liquid hole (B) of the top cover, the middle of the test strip bulges upward to form an “arch-bridge” structure with a horizontal plane.
    Type: Application
    Filed: July 15, 2020
    Publication date: September 1, 2022
    Inventor: Jing-Feng HUANG
  • Patent number: 11409202
    Abstract: Provided is a digital exposure control method, including: performing exposure of different types of functional areas of a substrate to be exposed through one or a plurality of full-page scans, wherein scan speeds for different types of functional areas of the substrate to be exposed are different.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 9, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xinglong Luan, Fuqiang Li, Jing Feng, Zhichong Wang, Peng Liu, Guangcai Yuan, Xue Dong
  • Publication number: 20220246460
    Abstract: The disclosure provides an apparatus for transferring LED chips, including: first light source configured to generate and emit first light rays; first support structure configured to carry load substrate, load substrate including light-transmissive substrate and the LED chips fixed on side of the light-transmissive substrate away from first light source by dissociation adhesive; second support structure configured to carry to-be-transferred substrate on side of the LED chips away from light-transmissive substrate; and optical control mechanism on side of light-transmissive substrate away from the LED chips and configured to control propagation direction of first light rays that irradiate onto first radiation region of the optical control mechanism to form target light rays that irradiate onto target radiation region of load substrate, so that dissociation adhesive in target radiation region is dissociated to transfer LED chips in target radiation region to to-be-transferred substrate.
    Type: Application
    Filed: September 29, 2021
    Publication date: August 4, 2022
    Inventors: Guangcai YUAN, Haixu LI, Xin GU, Jing FENG
  • Patent number: 11393378
    Abstract: A gate driving circuit unit, a gate driving circuit and a display device are provided. The gate driving circuit unit includes a pull-up node noise-reduction circuit and a pull-up control circuit. The pull-up node noise-reduction circuit is electrically connected to an input end, a pull-down node and a pull-up node, and configured to control the pull-up node to be electrically connected to, or electrically disconnected from, the input end under the control of a potential at the pull-down node. The pull-up control circuit is electrically connected to the pull-up node and the input end, and configured to control the pull-up node to be electrically connected to the input end at an input stage.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 19, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhichong Wang, Guangcai Yuan, Fuqiang Li, Liwei Liu, Jing Feng, Peng Liu, Xinglong Luan
  • Publication number: 20220188573
    Abstract: The present disclosure provides an end-to-end attention pooling-based classification method for histopathological images. The method specifically includes the following steps: S1, cutting the histopathology image into patches of a specified size, removing the patches with too much background area and packaging the remaining patches into a bag; S2, training a deep learning network by taking the bag obtained in S1 as an input using a standard multi-instance learning method; S3, scoring all the patches by using the trained deep learning network, and selecting m patches with highest and lowest scores for each whole slide image to form a new bag; S4, building a deep learning network including an attention pooling module, and training the network by using the new bag obtained in S3; and S5, after the histopathology image to be classified is processed in S1 and S3, performing classification by using the model obtained in S4.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 16, 2022
    Inventors: Juan Liu, Zhiqun Zuo, Yuqi Chen, Zhuoyu Li, Jing Feng
  • Patent number: 11361703
    Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 14, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peng Liu, Bailing Liu, Fuqiang Li, Zhichong Wang, Jing Feng, Xinglong Luan
  • Patent number: 11355920
    Abstract: An improved electric circuit structure for short circuit protection is applicable to examining a device under test, comprising a circuit breaking element, a thermistor, a filtering and rectifying module and a capacitor. A first end of the circuit breaking element is connected to a power source. The filtering and rectifying module is connected to a second end of the circuit breaking element, a ground, a first end of the thermistor and a first end of the capacitor. A second end of the capacitor is connected to a second end of the thermistor. The capacitor is connected in parallel with the device under test. The circuit breaking element disclosed in the present invention is a ceramic tube fuse and forms an open circuit when the device under test forms a short circuit. Meanwhile, the ceramic tube fuse withstands voltage between its first and second end without generating any physical damage.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 7, 2022
    Assignee: Leader Electronics
    Inventors: Shi-Guo Deng, Zuo-Quan Zhou, Jing Feng
  • Publication number: 20220157223
    Abstract: The present application discloses a pixel circuit and a driving method thereof, and a display device. The circuit includes: a first initialization sub-circuit, a data writing circuit, a light emitting control circuit, a capacitor circuit, a drive transistor, a compensation circuit, a light emitting element, and a holding circuit; the first initialization sub-circuit is connected to a second terminal of the capacitor circuit and a gate of the drive transistor; the data writing circuit and the holding circuit are connected to a first terminal of the capacitor circuit; the light emitting control circuit is connected to a first electrode of the light emitting element and a second electrode of the drive transistor; a first electrode of the drive transistor is connected to the first power supply; a second electrode of the light emitting element is connected to a second power supply.
    Type: Application
    Filed: June 23, 2021
    Publication date: May 19, 2022
    Inventors: Zhichong WANG, Xinglong LUAN, Peng LIU, Jing FENG, Gaoming SUN, Yi OUYANG
  • Publication number: 20220154347
    Abstract: The present disclosure belongs to the field of preparation technology and provides an ultralimit alloy and a preparation method therefor. The ultralimit alloy comprises an alloy matrix. A bonding layer and a ceramic layer are successively deposited on a surface of the alloy matrix. The alloy matrix includes one of a magnesium alloy matrix, an aluminium alloy matrix, a titanium alloy matrix, an iron alloy matrix, a nickel alloy matrix, a copper alloy matrix, a zirconium alloy, and a tin alloy. For an ultralimit magnesium alloy, an ultralimit aluminium alloy, an ultralimit nickel alloy, an ultralimit titanium alloy, an ultralimit iron alloy and an ultralimit copper alloy, the bonding layer is a composite bonding layer, the ceramic layer is a composite ceramic layer, and the outside of the composite ceramic layer is further successively deposited with a reflecting layer, a catadioptric layer, an insulating layer and a carbon foam layer.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 19, 2022
    Applicant: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: JING FENG, FUSHUO WU, QI ZHENG, KAILONG YANG, CHAO LI, PENG SONG, XIAOYU CHONG, ZHENHUA GE, LIN CHEN, JUN WANG
  • Publication number: 20220144705
    Abstract: The present disclosure discloses a rare earth tantalate ceramic resisting corrosion of a low melting point oxide. A general chemical formula of the ceramic is RETaO4. A method for preparing the ceramic includes: weighing RE2O3 powder and Ta2O5 powder and adding to a solvent to mix, and ball milling the mixed solution with a ball mill to obtain powder A; drying the powder A, and sieving the powder A for a first time to obtain powder B; placing the powder B in a mold for compaction, pre-sintering the powder B to form a block C, cooling the block C to room temperature, grounding the block C with a grinder, and sieving the block C for a second time to obtain powder D; and sintering the powder D to obtain the rare earth tantalate ceramic. The ceramic has high density and strong corrosion resistance to low melting point oxides.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 12, 2022
    Applicant: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: JING FENG, LIN CHEN, XIAOYU CHONG, JUN WANG
  • Patent number: 11328652
    Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 10, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peng Liu, Bailing Liu, Fuqiang Li, Zhichong Wang, Jing Feng, Xinglong Luan
  • Publication number: 20220137515
    Abstract: A digital exposure apparatus includes a lens array, the lens array at least including a first lens unit and a second lens unit, a light transposition assembly arranged on an exit light path of the second lens unit, and the light transposition assembly being used for controlling a light exiting from the second lens unit to be transposed with respect to an exposure direction of the digital exposure apparatus. When the digital exposure apparatus is used for exposure, a light passing through the first lens unit and a light penetrating through the second lens unit are needed to expose the same position for multiple times.
    Type: Application
    Filed: March 26, 2021
    Publication date: May 5, 2022
    Inventors: Jing FENG, Xinglong LUAN, Zhichong WANG, Peng LIU, Guangcai YUAN
  • Publication number: 20220130310
    Abstract: A gate driving circuit unit, a gate driving circuit and a display device are provided. The gate driving circuit unit includes a pull-up node noise-reduction circuit and a pull-up control circuit. The pull-up node noise-reduction circuit is electrically connected to an input end, a pull-down node and a pull-up node, and configured to control the pull-up node to be electrically connected to, or electrically disconnected from, the input end under the control of a potential at the pull-down node. The pull-up control circuit is electrically connected to the pull-up node and the input end, and configured to control the pull-up node to be electrically connected to the input end at an input stage.
    Type: Application
    Filed: June 23, 2021
    Publication date: April 28, 2022
    Inventors: Zhichong WANG, Guangcai YUAN, Fuqiang LI, Liwei LIU, Jing FENG, Peng LIU, Xinglong LUAN
  • Publication number: 20220130309
    Abstract: A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.
    Type: Application
    Filed: June 23, 2021
    Publication date: April 28, 2022
    Inventors: Zhichong WANG, Guangcai YUAN, Fuqiang LI, Jing FENG, Xinglong LUAN, Peng LIU
  • Patent number: 11308838
    Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 19, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhichong Wang, Fuqiang Li, Jing Feng, Peng Liu, Xinglong Luan
  • Publication number: 20220112132
    Abstract: The present disclosure relates to the technical field of ceramic powder preparation, and discloses a zirconia/titania/cerium oxide doped rare earth tantalum/niobate RETa/NbO4 ceramic powder and a preparation method thereof. A general chemical formula of the ceramic powder is RE1-x(Ta/Nb)1-x(Zr/Ce/Ti)2xO4, 0<x<1, the crystal structure of the ceramic powder is orthorhombic, the lattice space group of the ceramic powder is C2221, the particle size of the ceramic powder ranges from 10 to 70 ?m, and particles of the ceramic powder are spherical. During preparation, the raw materials are ball-milled before a high temperature solid phase reaction, then mixed with a solvent and an organic binder to obtain a slurry C, then centrifuged and atomized to obtain dry pellets, and finally sintered to obtain a zirconia/titanium oxide/cerium oxide doped rare earth tantalum/niobate RETa/NbO4 ceramic powder, which satisfies the requirements of APS technology for ceramic powders.
    Type: Application
    Filed: January 8, 2019
    Publication date: April 14, 2022
    Applicant: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: JING FENG, PENG WU, ZHENHUA GE, PENG SONG, LIN CHEN, JUN WANG
  • Publication number: 20220106234
    Abstract: The present disclosure provides a high-entropy rare earth-toughened tantalate ceramic. The ceramic is prepared by sintering Ta2O5 powder and x types of different RE2O3 powder, 4?x?9, and the molar ratio of the RE2O3 powders is 1. RE2O3 powder and Ta2O5 powder having the molar ratio of RE to Ta being 1:1 are weighed, a solvent is added for mixing, and ball milling is performed by a ball mill to obtain mixed powder M; the powder M is dried at a temperature of 650-850° C. for 1.5-2 h to obtain dried powder; the powder is sieved to obtain powder N, the powder N is placed in a mold for first pressing to obtain a rough blank, and the rough blank is then pressed for the second time to obtain a compact blank; the compact blank is sintered to obtain the high-entropy rare earth-toughened tantalate ceramic.
    Type: Application
    Filed: November 12, 2019
    Publication date: April 7, 2022
    Applicant: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: JING FENG, YUNXUAN ZHOU, XIAOYU CHONG, PENG WU, LIN CHEN, JUN WANG