Abstract: Disclosed herein are technologies related to database calculation that utilizes parallel-computation of tasks in a directed acyclic graph. In accordance with one aspect, dependency of tasks is converted into a directed acyclic graph that topologically orders the tasks into layers of tasks. A database calculation may be performed, wherein the database calculation computes in parallel the tasks in each layer of the layers of tasks.

Abstract: A controlling apparatus and method for an electric drive transmission used in a dual-motor electric vehicle are disclosed, wherein when the second motor is in the zero torque state, the synchronizer is shifted to a neutral position, the second motor the required torque being kept to be zero; after shifted to the neutral position, if the target gear position is the neutral position, gearshifting is completed, an if the target gear position is not the neutral position, speed control to the second motor is conducted to adjust its speed towards a target speed; once the second motor is adjusted to the target speed, the second motor is subjected to zero torque control, the second motor the required torque being zero; once the second motor comes into a zero torque state, the synchronizer is shifted to a target gear position, the required torque of the second motor being kept to be zero; once the synchronizer is located in the target gear position, the required torque of the second motor changes towards a target valu

Abstract: An apparatus includes a display panel. In one example, the display panel includes an array of subpixels in a first, a second, and a third colors. Subpixels in the first, second, and third colors are alternatively arranged in every three adjacent rows of the array of subpixels. Every two adjacent rows of the array of subpixels are staggered with each other. A first subpixel in one of the first, second, and third colors and a second subpixel in a same color as the first subpixel are offset by 3 units in the horizontal axis and 4 units in the vertical axis. The first and second subpixels have a minimum distance among subpixels in the same color.

Abstract: An apparatus including a display and control logic. In one example, the display includes an array of subpixel groups. Each of the subpixel groups includes one subpixel in a first color, two subpixels in a second color, and two subpixels in a third color. Subpixel groups in each row of the array are repeated. Subpixel groups in each row of the array are staggered relative to subpixels groups in an adjacent row of the array. The control logic is operatively coupled to the display and configured to receive display data and convert the display data into control signals for driving the array of subpixel groups.

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display.

Abstract: An automated database analyzer is uses templates to accommodate multiple database languages, such as SQL and its dialects. The templates are combined with metadata that define a database schema and operations on the database schema. An SQL file instantiates the database schema on a database system being tested. Operations on the database schema may then be performed to assess the performance of the database system being tested.

Abstract: Method and apparatus for subpixel rendering. In one example, for each of an array of pixels on a display, a first signal including a first set of components is received. The first set of components are converted to a second set of components. The second set of components include a first component representing a first attribute of the pixel and a second component representing a second attribute of the pixel. The second set of components of the first signal are modified to generate a second signal by applying at least one operation to at least one of the first and second components based on the corresponding attribute of the pixel. The modified second set of components are converted to a modified first set of components of the second signal. A third signal is generated based on the modified first set of components for rendering subpixels corresponding to the pixel.

Abstract: A memory circuit is provided, including: a plurality of sectors, where each sector includes at least two parallel rows of memory units; a first control line, a second control line and a word line corresponding to each row of memory units, where at least two of the first control lines which are in the same sector and neighboring with each other are connected, and at least two of the second control lines which are in the same sector and neighboring with each other are connected; and a plurality of bit lines perpendicular with the word lines. The number of the first and second control lines may be reduced, so decoding units which control the control lines may occupy less chip areas, thereby reducing chip areas occupied by the memory circuit.

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a subpixel repeating group tiled across the display in a regular pattern. The subpixel repeating group comprises n rows of subpixels and n columns of subpixels. Each row of the subpixel repeating group comprises n types of subpixels. Each column of the subpixel repeating group comprises the n types of subpixels. Subpixels along each diagonal direction of the subpixel repeating group comprise at least two types of the n types of subpixels. The control logic is operatively coupled to the display and is configured to receive display data and render the display data into control signals for driving the array of subpixels of the display.

Abstract: Display devices and methods for making and driving the display devices. In one example, a device for display includes an array of pixels for display. Each of the pixels includes a first light emitting element and a second light emitting element. The first light emitting element is formed on a substrate. The second light emitting element is formed on the first light emitting element. The first and second light emitting elements share a same electrode.

Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) and an EEPROM storage array are provided. The EEPROM storage array includes: at least one storage area, wherein the storage area comprises M word lines in a row direction, 8 bit lines in a column direction, 8 source lines in the column direction, and a plurality of storage units arranged in M rows and 8 columns, where M is a positive integer; and wherein gate electrodes of storage units in a same row are connected with a same word line, drain electrodes of storage units in a same column are connected with a same bit line, and source electrodes of storage units in a same column are connected with a same source line. The EEPROM's volume is reduced by connecting source electrodes of storage units in a same column to a same source line, and arranging the source lines in a column direction.

Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) and an EEPROM storage array are provided. The EEPROM storage array includes: at least one storage area, wherein the storage area includes M word lines in a row direction, 8 bit lines in a column direction, N source lines in the row direction, and a plurality of storage units arranged in M rows and 8 columns; wherein M and N are positive integers; and wherein gate electrodes of storage units in a same row are connected with a same word line, source electrodes of storage units in every two adjacent rows are connected with a same source line, and drain electrodes of storage units in a same column are connected with a same bit line. There is no need to perform a decoding operation on source lines of the EEPROM and the EEPROM storage array, and a volume of the EEPROM is reduced.

Abstract: Disclosed herein are technologies related to database calculation that utilizes parallel-computation of tasks in a directed acyclic graph. In accordance with one aspect, dependency of tasks is converted into a directed acyclic graph that topologically orders the tasks into layers of tasks. A database calculation may be performed, wherein the database calculation computes in parallel the tasks in each layer of the layers of tasks.

Abstract: A method of controlling a memory array is provided. The memory array includes memory cells, first control lines, second control lines, parallel bit lines and word lines that are perpendicular to the bit lines and are electrically insulated therefrom. The method includes selecting one or more of the memory cells and enabling a reading, a programming or an erasing operation on the selected memory cell(s) by applying different voltages respectively to word line(s), first control line(s) and second control line(s), connected to the selected memory cell(s), bit line(s) connected to source(s) of the selected memory cell(s) and bit line(s) connected to drain(s) of the selected memory cell(s), wherein the remaining one(s) of the first and second control line(s) that are connected to the unselected one(s) of the memory cell(s), is applied with a minus voltage ranging from ?3 V to ?0.5 V.

Abstract: An apparatus includes control logic and a scan driving unit. The control logic is configured to control driving of a display panel having an array of pixels divided into groups of pixels. Each group of pixies includes rows of pixels. The control logic is configured to control sequentially applying of multiple backlights having different colors to the array of pixels in multiple time periods. The scan driving unit is operatively coupled to the control logic and is configured to, in each time period, scan the rows of pixels of each group of pixels according to a row scanning sequence. For each group of pixels, in a first time period, the scan driving unit sequentially scans the rows of pixels according to a first row scanning sequence; in a second time period, the scan driving unit sequentially scans the rows of pixels according to a second row scanning sequence.

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display.

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display.

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.