Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: The present disclosure describes methods, systems, and computer program products for generic process modeling. One method includes identifying a business process for execution, the business process defined by one or more process steps, identifying a process routing table associated with the identified business process, at least a portion of the process routing table including one or more entries defining a set of business process rules for the identified business process, identifying a particular entry in the process routing table associated with a current state of the identified business process; and performing at least one action defined by the identified particular entry in the process routing table. In some instances, at least one entry in the process routing table is associated with one of a plurality of process patterns, with each process pattern comprising a reusable, predefined operation.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory circuit is provided, including: a plurality of sectors, where each sector includes at least two parallel rows of memory units; a first control line, a second control line and a word line corresponding to each row of memory units, where at least two of the first control lines which are in the same sector and neighboring with each other are connected, and at least two of the second control lines which are in the same sector and neighboring with each other are connected; and a plurality of bit lines perpendicular with the word lines. The number of the first and second control lines may be reduced, so decoding units which control the control lines may occupy less chip areas, thereby reducing chip areas occupied by the memory circuit.

Abstract: An automated database analyzer is uses templates to accommodate multiple database languages, such as SQL and its dialects. The templates are combined with metadata that define a database schema and operations on the database schema. An SQL file instantiates the database schema on a database system being tested. Operations on the database schema may then be performed to assess the performance of the database system being tested.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: Systems, methods and media are provided for presenting a group of available broadcast channels utilizing a wireless network upon initiation of a channel-viewing graphical user interface (GUI). The group comprises channels that can be broadcast most efficiently to the mobile device. After initiating the channel-viewing GUI on the mobile device, requests are communicated to elements on the network to retrieve lists of currently broadcast channels in the area and currently viewed channels throughout the wireless network. A list also is retrieved of recently viewed channels on the mobile device. At least a portion of each list is then presented on the channel-viewing GUI. The lists can be sent by a first video media proxy (VMP) server and a broadcast management server (BMS).

Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

Abstract: A data model that allows for relationships between entities, also referred to as parties, to be modeled as attributes of an entity and for customization of the data model in a manner that facilitates upgrading of the data model. In some embodiments, the data model may facilitate creation and processing of financial applications. Using the data model, received application data can be stored in a financial application record, including data relating to a party's financial statements. In some embodiments, the data model may facilitate management of financial account data for multiple accounts. In some embodiments the data model may facilitate management of credit information, such as credit information collected by credit bureaus.

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a subpixel repeating group tiled across the display in a regular pattern. The subpixel repeating group comprises n rows of subpixels and n columns of subpixels. Each row of the subpixel repeating group comprises n types of subpixels. Each column of the subpixel repeating group comprises the n types of subpixels. Subpixels along each diagonal direction of the subpixel repeating group comprise at least two types of the n types of subpixels. The control logic is operatively coupled to the display and is configured to receive display data and render the display data into control signals for driving the array of subpixels of the display.

Abstract: The present disclosure describes methods, systems, and computer program products for generic process modeling. One method includes identifying a business process for execution, the business process defined by one or more process steps, identifying a process routing table associated with the identified business process, at least a portion of the process routing table including one or more entries defining a set of business process rules for the identified business process, identifying a particular entry in the process routing table associated with a current state of the identified business process; and performing at least one action defined by the identified particular entry in the process routing table. In some instances, at least one entry in the process routing table is associated with one of a plurality of process patterns, with each process pattern comprising a reusable, predefined operation.

Abstract: Systems, methods and media are provided for presenting a group of available broadcast channels utilizing a wireless network upon initiation of a channel-viewing graphical user interface (GUI). The group comprises channels that can be broadcast most efficiently to the mobile device. After initiating the channel-viewing GUI on the mobile device, requests are communicated to elements on the network to retrieve lists of currently broadcast channels in the area and currently viewed channels throughout the wireless network. A list also is retrieved of recently viewed channels on the mobile device. At least a portion of each list is then presented on the channel-viewing GUI. The lists can be sent by a first video media proxy (VMP) server and a broadcast management server (BMS).

Abstract: An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: Methods, systems, and media are provided for rights protection of an instance of media content in a hybrid downloading and streaming media environment. A request from a device to download an instance of media content is communicated. Verification is obtained as to whether or not the device is authorized to receive and execute the instance. The instance of media content is streamed so that portions may be downloaded. The instance of media content also includes interspersed, non-storable authorization information. When subsequent execution of the instance of stored media content is attempted, a subsequent request for the authorization information is communicated. Only the authorization information is streamed for the subsequent request, allowing execution without burdening network resources with data-intensive streams.

Abstract: A method and assay for predicting athletic performance potential of a subject, such as a thoroughbred race horse, comprising the steps of assaying a biological sample from a subject for the presence of a single nucleotide polymorphism in one or more genes associated with athletic performance. The athletic performance genes may be selected from one or more of MSTN, COX4I2, PDK4, CKM and COX4I1.

Abstract: A gate-separated type flash memory with a shared word line includes: a semiconductor substrate, on which a source electrode area and a drain electrode area are separately arranged; a word line, which is arranged between the source electrode area and the drain electrode area; a first storage bit unit, which is arranged between the word line and the source electrode area, and a second storage bit unit, which is arranged between the word line and the drain electrode area. The two storage bit units and word line are separated by a tunneling oxide layer. The two storage bit units respectively have a first control gate, a first floating gate and a second control gate, a second floating gate, and the two control gates are separately respectively arranged on two floating gates.