Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Abstract: In one embodiment, a method includes receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Abstract: Lung cancer is one of the most commonly diagnosed cancers in the world. While numerous predictive genetic models of non-small cell lung cancer (NSCLC) have been proposed, but many current models fail to accurately predict patient survival when verified by other multiple datasets. Here, we successfully eliminated institutional variations and merged twelve datasets from different institutions to generate a training cohort of 1073 and a testing cohort of 659. From the training cohort, we identified 129 deferentially expressed probes or 95 genes (Table1-2) associated with Lung Cancer. Here we showed that using seven genes from Table1-2 and combined these genes values with the clinical parameters of age and cancer stage to design the Lung Cancer Prognostic Index (LCPI). Using the LCPI, we were able to differentiate patient populations into low, intermediate, and high risk groups and predict patient survival probabilities for all stages and all cell types of NSCLC at 10 and 15 years.

Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

Abstract: In one embodiment, a method includes recording, for each of a plurality of data frames, a virtual write address including a multiframe indicator and a byte number indicator; and reading a group of associated data frames identified by corresponding multiframe indicators and byte number indicators. The reading is based on determining a minimum write address from a plurality of physical write addresses in the group of associated data frames by comparing virtual write addresses of all members in the group.

Abstract: A protecting structure of an uninterruptible power supply prevents the uninterruptible power supply. The uninterruptible power supply device has a switch with a switching piece. The protecting structure includes a chassis, a sensor and a cover body. The chassis has an opening slot, the uninterruptible power supply device is installed in the chassis, and the switching piece is disposed corresponding to the opening slot. The sensor is provided on a side of the opening slot of the chassis and electrically connected with the uninterruptible power supply device. The cover body includes a cover plate and at least one blocking member connecting with the cover plate. The cover plate covers the opening slot, wherein the switching piece ejects the blocking member to expose the opening slot when the covered switching piece is switched from a first position to a second position.

Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

Abstract: The present invention relates to a method of fabricating a through silicon via (TSV) structure, in which, a dielectric layer is disposed to cover surface of each of a device region of a substrate and a sidewall and a bottom of a via hole in a TSV region of the substrate, and the via hole having the dielectric layer covering the sidewall and the bottom is filled with a conductive material. The present invention also relates to a TSV structure, in which, a dielectric layer disposed in the device region of a substrate extends to the via hole in a TSV region of the substrate to cover surface of the sidewall of the via hole to serve as a dielectric liner, and a conductive material is filled into the via hole having the dielectric layer covering the sidewall.

Abstract: The present invention relates to the discovery that specific human taste receptors in the T2R taste receptor family respond to particular bitter compounds present in, e.g., coffee. Also, the invention relates to the discovery of specific compounds and compositions containing that function as bitter taste blockers and the use thereof as bitter taste blockers or flavor modulators in, e.g., coffee and coffee flavored foods, beverages and medicaments. Also, the present invention relates to the discovery of a compound that antagonizes numerous different human T2Rs and the use thereof in assays and as a bitter taste blocker in compositions for ingestion by humans and animals.

Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

Abstract: An expansion card mounting assembly includes an expansion card and a chassis. The expansion card includes a slot cover having a fixing portion. The chassis includes a bottom plate and a rear plate. The rear plate includes a supporting piece. A flange is connected to a top edge of the rear plate. A first mounting member is mounted on the bottom plate. A second mounting member includes a first piece and a second piece. A bridge piece and a bent piece is connected to the second piece to surround an engaging space. The first piece of the second member presses the fixing portion of the expansion card on the supporting piece. The flange of the rear plate engages in the engaging space. The first mounting member secures an edge of the expansion card.

Abstract: The present invention relates to the discovery that specific human taste receptors in the T2R taste receptor family respond to particular bitter compounds present in, e.g., coffee. Also, the invention relates to the discovery of specific compounds and compositions containing that function as bitter taste blockers and the use thereof as bitter taste blockers or flavor modulators in, e.g., coffee and coffee flavored foods, beverages and medicaments. Also, the present invention relates to the discovery of a compound that antagonizes numerous different human T2Rs and the use thereof in assays and as a bitter taste blocker in compositions for ingestion by humans and animals.

Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.