Patents by Inventor Jing Ling

Jing Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060221944
    Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 5, 2006
    Inventors: Jing Ling, Soowan Suh, Juan-Carlos Calderon
  • Patent number: 7065628
    Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang
  • Patent number: 7061867
    Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Anguo T. Huang, Jing Ling, Jean-Michel Caia, Juan-Carlos Calderon, Vivek Joshi
  • Publication number: 20060020897
    Abstract: A method for showing a component on a user interface is disclosed. A style maker provides some style options, each style option including associated configurations. When constructing the component on the user interface, one of the style options is selected for showing the component. In this manner, the constructed component is distinctly displayed on the user interface responding to the respective event.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 26, 2006
    Inventor: Jing-Ling Li
  • Patent number: 6944728
    Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Jing Ling, Anguo T. Huang
  • Patent number: 6892284
    Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: May 10, 2005
    Assignee: Intel Corporation
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang, Steve J. Clohset
  • Publication number: 20040131069
    Abstract: A method and apparatus for providing a virtual output queue (VoQ) from a received set of data packets in a multi-service system. Each packet is divided into at least one partition, including a last partition that includes packet information, such as error status and packet length. The system receives the packet from a flow, parses the packet into partitions, including a first partition and the last partition, places each last partition into a linked list based on a time when the last partition was received, links the last partition to the first partition, and employs the linked list as the output queue. This system allows for rapid compilation and transmission of different sized packets, and obviates the need for the receiving processor to wait for the last partition to discard a bad packet.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Anguo T. Huang, Vivek Joshi
  • Publication number: 20040131055
    Abstract: A method and apparatus for managing multiple pointers is provided. Each pointer may be associated with a partition in a partitioned memory, such as DDR SDRAM used in a high speed networking environment. The system and method include a free pointer pool FIFO, wherein a predetermined quantity of pointers is allocated to the free pointer pool FIFO. The system selects one pointer from the free pointer pool FIFO when writing data to one partition in the partitioned memory, and provides one pointer to the free pointer pool FIFO when reading data from one partition in the partitioned memory. The system and method enable self balancing using the free pointer pool FIFO and decreases the number of memory accesses required. The system can be located on chip.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Jing Ling, Vivek Joshi, Anguo T. Huang
  • Publication number: 20040123056
    Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Jing Ling, Anguo T. Huang
  • Publication number: 20040049650
    Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.
    Type: Application
    Filed: September 11, 2002
    Publication date: March 11, 2004
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang, Steve J. Clohset
  • Publication number: 20040032920
    Abstract: Providing a noise signal comprises providing a first signal corresponding to a first band of a frequency spectrum of the noise signal. Next, providing a noise signal comprises providing a second signal corresponding to a second band of the frequency spectrum of the noise signal, the second signal based on the first signal. And finally, the first signal and the second signal are summed to provide the noise signal.
    Type: Application
    Filed: October 1, 2002
    Publication date: February 19, 2004
    Applicant: Industrial Technology Research Institute.
    Inventors: Fang-Chu Chen, Jing-Ling Tsai
  • Publication number: 20030225991
    Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Juan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang
  • Publication number: 20030223442
    Abstract: Network applications may require a guaranteed rate of throughput, which may be accomplished by using buffer memory reservation to manage a data queue used to store incoming packets. Buffer memory reservation reserves a portion of a data queue as a dedicated queue for each flow, reserves another portion of a data queue as a shared queue, and associates a portion of the shared queue with each flow. The amount of the buffer memory reserved by the dedicated queue sizes and the shared queue portion sizes for all of the flows may exceed the amount of physical memory available to buffer incoming packets.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Anguo T. Huang, Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Vivek Joshi
  • Publication number: 20030206522
    Abstract: A rate policing algorithm for packet flows is based on counters and threshold checking. The rate policing algorithm utilizes a state machine having four links: (1) compliant state to compliant state; (2) transition from compliant state to non-compliant state; (3) non-compliant state to non-compliant state; and (4) transition from non-compliant state to compliant state. Depending on the values obtained from the counters and utilizing the threshold values, it is determined whether a flow rate for packets is compliant or non-compliant.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventors: Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Vivek Joshi, Anguo T. Huang
  • Publication number: 20030185155
    Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 2, 2003
    Inventors: Anguo T. Huang, Jing Ling, Jean-Michel Caia, Juan-Carlos Calderon, Vivek Joshi
  • Patent number: 6433017
    Abstract: In accordance with the present invention, there are provided amphiphilic polyamine compounds and derivatives thereof having the property of promoting transfection of polynucleotides and polypeptides into cells, and formulations comprising said compounds.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 13, 2002
    Assignee: Gene Therapy Systems, Inc.
    Inventors: Philip L. Felgner, Xiang Gao, Jing Ling
  • Publication number: 20020106400
    Abstract: A calendered hydrocolloid dressing for the wound care and a one step method of manufacturing the hydrocolloidal dressing are described. In particular, the invention is concerned with a hydrocolloid dressing which is absorbent, non-damaging to the skin and comfortable to the user preferably having at least a thermoplastic elastomer backing and water absorbent polymeric adhesive layer.
    Type: Application
    Filed: August 8, 2001
    Publication date: August 8, 2002
    Inventors: Scott C. Barnes, Jing Ling Ding
  • Patent number: 6348499
    Abstract: Amphiphilic polyamide compounds and derivatives thereof having the property of promoting transfection of polynucleotides and polypeptides into cells, and formulations comprising said compounds.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: February 19, 2002
    Assignee: Gene Therapy Systems, Inc.
    Inventors: Philip L. Felgner, Xiang Gao, Jing Ling