Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

Abstract: The present disclosure provides IL-10 muteins and use of IL-10 muteins in fusion proteins. The IL-10 mutein or the fusion protein comprise one or more substitution on amino acids in position 104, position 107, and a combination thereof, relative to amino acids of wild-type IL-10. Advantageously, the IL-10 mutein or the fusion protein thereof are provided with reduced aggregation potency during purification and extended half-life.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a fin-like structure over a substrate; forming an isolation feature in the substrate and adjacent to the fin-like structure substrate; forming a dummy gate structure across the fin-like structure, where the dummy gate structure comprises a first portion disposed directly over the fin-like structure and a second portion disposed directly over a portion of the isolation feature; forming a mask film to cover the first portion of the dummy gate structure while exposing the second portion of the dummy gate structure; removing the second portion of the dummy gate structure and the portion of the isolation feature thereunder to form a gate isolation trench; forming a gate isolation structure in the gate isolation trench; and replacing the first portion of the dummy gate structure with a gate stack.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

Abstract: A method includes receiving, at a user device, a user selection entered into a third-party application to have a payload delivered to a delivery location via an uncrewed aerial vehicle (UAV). The method also includes displaying, by the user device within the third-party application, a first UI portion of a delivery software development kit (SDK). The first UI portion enables user selection of a delivery point at the delivery location. The method additionally includes after user selection of the delivery point, receiving, at the user device, a delivery status update from the delivery SDK indicating that the UAV has commenced delivery of the payload. The method also includes displaying, by the user device within the third-party application, a second UI portion of the delivery SDK. The second UI portion displays UAV tracking information as the UAV delivers the payload to the selected delivery point at the delivery location.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. one of the cells which is coupled to one of the first input pads and one of the second input pads is turned on, and a current flowing through the turned-on cell is measured.

Abstract: Systems and methods of generating electrical current from at least one photovoltaic cell are described herein. In some embodiments, a dual-cell arrangement of photovoltaic cells may be disposed on a face. Equal parts of a first photovoltaic cell and a second photovoltaic cell may be disposed on the face such that when a portion of the face is shaded, the first photovoltaic cell and the second photovoltaic cell receive substantially equal amounts of electromagnetic radiation. In some embodiments, the first photovoltaic cell and the second photovoltaic cell comprises a plurality of sub-cell connected in series and parallel to optimize the power output form the partially exposed cells.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: The present invention provides a sewage treatment biological agent and a preparation method and application thereof. The sewage treatment biological agent according to an embodiment of the present invention includes an induced nucleus. The induced nucleus has good bioaffinity. A microbial flora can be attached to the induced nucleus to achieve rapid growth. As the microbial flora gathers and grows on the induced nucleus, the granulation is gradually achieved by the sewage treatment biological agent to facilitate the sewage treatment. The microbial flora grows on the induced nucleus, and the growth process of microbial flora is a covering growth process which starts from the induced nucleus and gradually expands outward and centers on the induced nucleus. During the growth of microbial flora, extracellular polymers are secreted, which can further promote the granulation process by the sewage treatment biological agent.

Abstract: The present disclosure provides an IL-10 variant protein, a fusion protein comprising the IL-10 variant protein and a polypeptide, and the use thereof. The present disclosure also provides a method of producing the same and a pharmaceutical composition comprising the same.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.

Abstract: Systems and methods of generating electrical current from at least one photovoltaic cell are described herein. In some embodiments, a dual-cell arrangement of photovoltaic cells may be disposed on a face. Equal parts of a first photovoltaic cell and a second photovoltaic cell may be disposed on the face such that when a portion of the face is shaded, the first photovoltaic cell and the second photovoltaic cell receive substantially equal amounts of electromagnetic radiation. In some embodiments, the first photovoltaic cell and the second photovoltaic cell comprises a plurality of sub-cell connected in series and parallel to optimize the power output form the partially exposed cells.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.

Abstract: Test structures on a wafer are provided. A plurality of cells are arranged in rows and columns of a test array. First and second output pads are formed on opposite sides of the test array. A first output pad is coupled to the cells in one half of the rows of the test array. A second output pad is coupled to the cells in the other half of the rows of the test array. Each first input pad is coupled to the cells in respective column of the test array. Each second input pad is coupled to the cells in respective row of the test array. When a first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads, current flowing through the turned-on cell is measured through the first or second output pad.