Patents by Inventor Jinge YAO

Jinge YAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200248510
    Abstract: An internally threaded bit for percussion drilling is provided, which has thread roots wider than the thread crests. The bit exhibits a reduced rate of ringing off, and can accept drill rods having a range of crest widths.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Applicant: Hardrock Innovations Inc.
    Inventor: James Jing Yao
  • Publication number: 20200245456
    Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 30, 2020
    Inventors: Ho-Chieh Yu, Chen-Cheng-Lung Liao, Chun-Yu Lin, Hsiao-Ming Chang, Jing-Yao Chang, Tao-Chih Chang
  • Patent number: 10672677
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 2, 2020
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, WIN-HOUSE ELECTRONIC CO., LTD.
    Inventors: Jing-Yao Chang, Tao-Chih Chang, Kuo-Shu Kao, Fang-Jun Leu, Hsin-Han Lin, Chih-Ming Tzeng, Hsiao-Ming Chang, Chih-Ming Shen
  • Patent number: 10490478
    Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 26, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Kuo-Shu Kao, Jing-Yao Chang, Tao-Chih Chang
  • Publication number: 20180358307
    Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 13, 2018
    Inventors: Jing-Yao Chang, Tao-Chih Chang, Fang-Jun Leu, Wei-Kuo Han, Kuo-Shu Kao
  • Publication number: 20180261519
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co., Ltd.
    Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
  • Publication number: 20180233477
    Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 16, 2018
    Inventors: Jing-Yao Chang, Tao-Chih Chang, Fang-Jun Leu, Wei-Kuo Han, Kuo-Shu Kao
  • Patent number: 9970395
    Abstract: The present invention provides an admission pipe structure for automobile air admission, wherein internal part in pipe body of admission pipe includes channel, admission hole and exit hole formed on two sides of the channel are installed with first sleeve connection part and second sleeve connection part, and first sleeve connection part and second sleeve connection part are respectively sleeved onto exit connector and admission connector of the admission manifold pipe such that buckling component can be set up in penetration into two through-grooves installed in outer surface of second sleeve connection part thereby using buckling component to block at ring-shaped groove for fixedly positioning. When compressed air coming from the central cooler enters into admission pipe, compressed air can be smoothly guided by arc-shaped channel in pipe body, and aluminum alloy materials in admission pipe itself can prevent damages caused by the high-speed airflow of the compressed air.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 15, 2018
    Assignee: SPACE GEAR INDUSTRIAL LTD.
    Inventor: Jing-Yao Huang
  • Patent number: 9940415
    Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 10, 2018
    Assignee: ESS Technology, Inc.
    Inventors: A. Martin Mallinson, Hu Jing Yao, Dustin Forman
  • Publication number: 20180019178
    Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 18, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Kuo-Shu Kao, Jing-Yao Chang, Tao-Chih Chang
  • Patent number: 9706656
    Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 11, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Shih-Hsien Wu, Jing-Yao Chang, Tao-Chih Chang, Ren-Shin Cheng, Min-Lin Lee
  • Publication number: 20170084521
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Application
    Filed: May 4, 2016
    Publication date: March 23, 2017
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co.,Ltd.
    Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
  • Publication number: 20170082072
    Abstract: The present invention provides an admission pipe structure for automobile air admission, wherein internal part in pipe body of admission pipe includes channel, admission hole and exit hole formed on two sides of the channel are installed with first sleeve connection part and second sleeve connection part, and first sleeve connection part and second sleeve connection part are respectively sleeved onto exit connector and admission connector of the admission manifold pipe such that buckling component can be set up in penetration into two through-grooves installed in outer surface of second sleeve connection part thereby using buckling component to block at ring-shaped groove for fixedly positioning. When compressed air coming from the central cooler enters into admission pipe, compressed air can be smoothly guided by arc-shaped channel in pipe body, and aluminum alloy materials in admission pipe itself can prevent damages caused by the high-speed airflow of the compressed air.
    Type: Application
    Filed: May 24, 2016
    Publication date: March 23, 2017
    Inventor: Jing-Yao HUANG
  • Patent number: 9484315
    Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 1, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang
  • Publication number: 20160174360
    Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.
    Type: Application
    Filed: November 24, 2015
    Publication date: June 16, 2016
    Inventors: Chien-Min HSU, Shih-Hsien WU, Jing-Yao CHANG, Tao-Chih CHANG, Ren-Shin CHENG, Min-Lin LEE
  • Publication number: 20160163665
    Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
    Type: Application
    Filed: March 26, 2015
    Publication date: June 9, 2016
    Inventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang
  • Publication number: 20160154914
    Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 2, 2016
    Inventors: A. Martin Mallinson, Hu Jing Yao, Dustin Forman
  • Patent number: 9287851
    Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 15, 2016
    Assignee: ESS Technology, Inc.
    Inventors: A. Martin Mallinson, Hu Jing Yao, Dustin Forman
  • Patent number: 9240370
    Abstract: A power module includes a first substrate, at least two power elements, at least one conductive structure and at least one leadframe. The first substrate includes a first dielectric layer and two first metal layers. The first dielectric layer has at least two concavities and two opposite surfaces, the two first metal layers are respectively disposed on the two surfaces, and the two concavities are respectively formed on the two surfaces. The two power elements are respectively embedded in the two concavities of the first dielectric layer. The two power elements are electrically connected to each other through the conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 19, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Jung Yang, Yu-Lin Chao, June-Chien Chang, Jing-Yao Chang
  • Patent number: 9065384
    Abstract: A system and method is disclosed for selecting between two electronic signals, one of high quality, such as music audio, and the other of low quality, such as telephone call audio, in a smart phone, tablet or other device. In one embodiment, when the low quality signal is to be used this is accomplished by disabling the amplifier output to disconnect the high quality audio signal from the output port, rather than by means of a switch between the amplifier and the output port as in the prior art. This eliminates degradation of the signal due to the switch when the high quality signal is to be used. The amplifier typically has an associated feedback resistor network, and this may also be disconnected by means of a switch when the low quality signal is to be used, thus preventing distortion of the low quality signal due to the feedback network being a parallel load to the output port.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 23, 2015
    Assignee: ESS Technology, Inc.
    Inventors: Robert L. Blair, Hu Jing Yao, Dustin Dale Forman, A. Martin Mallinson