Patents by Inventor Jinghong Li
Jinghong Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140312420Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.Type: ApplicationFiled: September 17, 2013Publication date: October 23, 2014Applicant: International Business Machines CorporationInventors: Thomas N. Adam, Veeraraghavan S. Basker, Jinghong Li, Chung-Hsun Lin, Sebastian Naczas, Alexander Reznicek, Tenko Yamashita
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Publication number: 20140070316Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Jinghong Li, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Qingyun Yang
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Patent number: 8666518Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.Type: GrantFiled: January 24, 2012Date of Patent: March 4, 2014Assignee: NeoPhotonics CorporationInventors: Anthony J. Ticknor, Jinghong Li, Robert Lombaerde
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Publication number: 20140027863Abstract: A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Thomas N. Adam, Keith E. Fogel, Jinghong Li, Alexander Reznicek
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Publication number: 20130270611Abstract: A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.Type: ApplicationFiled: April 13, 2012Publication date: October 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Jinghong Li, Alexander Reznicek
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Publication number: 20130193492Abstract: An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.Type: ApplicationFiled: January 30, 2012Publication date: August 1, 2013Applicant: International Business Machines CorporationInventors: THOMAS N. ADAM, Kangguo Cheng, Hong He, Ali Khakifirooz, Jinghong Li, Alexander Reznicek
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Patent number: 8421191Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.Type: GrantFiled: June 26, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu
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Patent number: 8410544Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.Type: GrantFiled: September 9, 2011Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Publication number: 20120305940Abstract: A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the <100> crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.Type: ApplicationFiled: June 1, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas N. Adam, Stephen W. Bedell, Bruce B. Doris, Lisa F. Edge, Keith E. Fogel, Johnathan E. Faltermeier, Jinghong Li, Alexander Reznicek, Devendra K. Sadana, Bin Yang
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Patent number: 8299535Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate.Type: GrantFiled: June 25, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jeffrey B. Johnson, Jinghong Li, Dae-Gyu Park, Zhengmao Zhu
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Publication number: 20120261717Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Applicant: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu
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Patent number: 8236660Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer.Type: GrantFiled: April 21, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu
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Publication number: 20120121251Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Applicant: NEOPHOTONICS CORPORATIONInventors: Anthony J. Ticknor, Jinghong Li, Robert Lombaerde
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Patent number: 8126577Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.Type: GrantFiled: October 9, 2008Date of Patent: February 28, 2012Assignee: NeoPhotonics CorporationInventors: Anthony J. Ticknor, Jinghong Li, Robert Lombaerde
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Publication number: 20110316044Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jeffrey B. Johnson, Jinghong Li, Dae-Gyu Park, Zhengmao Zhu
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Publication number: 20110316081Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.Type: ApplicationFiled: September 9, 2011Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Publication number: 20110260213Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer.Type: ApplicationFiled: April 21, 2010Publication date: October 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu
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Patent number: 8043920Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.Type: GrantFiled: September 17, 2009Date of Patent: October 25, 2011Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Thomas Safron Kanarsky, Jinghong Li, Christine Qiqing Ouyang, Dae-Gyu Park, Zhibin Ren, Xinhui Wang, Haizhou Yin
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Patent number: 8035141Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.Type: GrantFiled: October 28, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu
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Publication number: 20110095343Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu