Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner's response to changes in input data.

Abstract: A post PLL filter is coupled to the output terminal of a phase locked loop. The post PLL filter reduces the jitter of the PLL output clock signal by increasing the Q of the phase locked loop. In addition, some embodiments of the present invention also provides amplitude magnification of the PLL output clock signal.

Abstract: An integrated circuit driver provides, among other things, a high data communication rate, a large common mode output voltage range, avoidance of spikethrough current that increases power consumption, improved switching speed using current-steering techniques, and improved matching of steady-state output current in the high logic state to that of the low logic state. The driver includes complementary differential pairs and associated current mirror circuits that differentially source/sink current at a pair of load conductors to drive the load conductors into a logic state. A single-ended embodiment is also described.

Abstract: An integrated circuit driver provides, among other things, a high data communication rate, a large common mode output voltage range, avoidance of spikethrough current that increases power consumption, improved switching speed using current-steering techniques, and improved matching of steady-state output current in the high logic state to that of the low logic state. The driver includes complementary differential pairs and associated current mirror circuits that differentially source/sink current at a pair of load conductors to drive the load conductors into a logic state. A single-ended embodiment is also described.

Abstract: A voice or data transmission system and specifically an interpolation filter used within the transmission system is provided for producing either fractional or integer interpolation ratios. The digital signal resulting from the interpolation filter has a relatively high signal to noise ratio whenever fractional interpolation is needed. The interpolation filter includes multiple stages coupled in series, and an integer interpolation branch switched in parallel with a fractional interpolation branch. A controller determines whether the integer or fractional interpolation ratio is needed based on maintaining a fixed oversampling data rate from the interpolation filter given a changing incoming sampling rate. If the incoming sampling rate should require fractional interpolation, then a branch implementing fractional interpolation ratio is used in lieu of the integer interpolation ratio.

Abstract: A comb filter is provided for achieving substantial attenuation of aliasing or imaging bans of a signal to be filtered. The comb filter can perform decimation or interpolation, depending upon its application. Integration can include an integration term with adjustable voltage accumulation at a particular sample point in time. The accumulation factor can be an integer or fractional number and is introduced at a sample count value L within each of M number of samples formed by the rate change switch within the comb filter. The amount of gain being introduced can possibly vary depending on the number of accumulation cycles programmed within configuration registers of the digital signal processor which carries out the comb filter functions. The programmable accumulator avoids having to implement a multiplication operation and the complexities associated therewith.

Abstract: An analog-to-digital converter is provided for producing digital signal representative of analog signals. Noise induced upon the digital signals can be substantially removed using a digital decimation filter. The decimation filter includes a front-end portion which receives the digital data at a relatively high sample rate and performs filtering operations with minimal complexity. Preferably, the front-end portion includes at least one stage of filtering and more preferably at least two filter stages, each of which perform interpolation separate from decimation. According to one embodiment, the first stage of the front-end portion involves decimation and the latter stage or stages of that portion involves a combination of interpolation and decimation. The cumulative effect is to reduce the sample rate of the incoming data stream produced by, for example, a quantizer to a value which can be more easily manipulated by the back-end portion of the digital decimation filter.