Abstract: A display panel includes an active area; a fanout region; and a bonding region located on one side of the fanout region away from the active area. A driver chip is disposed in the bonding region. The driver chip includes a first side edge adjacent to the fanout region, a second side edge opposite to the first side edge, and two third side edges. The driver chip includes a plurality of output terminals disposed close to the first side edge. The display panel includes: a plurality of fanout lines located in the fanout region; and a plurality of gull-wing lines located in the bonding region. Part of the fanout lines extend from the fanout region to a region where the first side edge is located, and are electrically connected to the output terminals. Another part of the fanout lines are electrically connected to the output terminals via the gull-wing lines.

Abstract: An array substrate and a display device are provided. The array substrate includes a display area and a non-display area that at least partially surrounds the display area; the non-display area includes at least two clock signal lines, wherein a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3.

Abstract: A method for analyzing environmental sounds to identify repeating noises due to power equipment for purposes of controlling noise pollution is disclosed. Ambient sounds are sampled with microphones and the resulting data analyzed by an edge computing device. The samples are compared to stored data with a convolutional neural network by the edge computing device which also performs pitch shifting and cycle shifting to reduce false negatives. Positive results are reported via LoRa and/or 4G to a cloud platform and/or backend server.

Abstract: An includes a display area and a non-display area that at least partially surrounds the display area; the non-display area includes at least two clock signal lines, wherein a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3.

Abstract: Provided are multilayer structures and articles comprising same. The multilayer structure comprises: a biaxially-oriented polyethylene film comprising a skin layer with a matte surface and a core, the core comprising one or more core layers; a sealant film; and an adhesive adhering the sealant film to the matte surface of the skin layer of the biaxially-oriented polyethylene film. The multilayer structure can exhibit an enhanced adhesive bonding force in comparison to other multilayer structures.

Abstract: An array base plate and a display apparatus are provided by the present application. The array base plate includes a substrate, an active area and a binding area that are located on the substrate, wherein the binding area is located at one side of the active area; the array base plate further includes: an alignment layer extending from the active area to the binding area; and binding terminals located in the binding area, wherein an orthographic projection of the alignment layer on the substrate does not overlap with orthographic projections of the binding terminals on the substrate; wherein in a direction parallel to a plane where the substrate is located and pointing from the active area to the binding area.

Abstract: The present disclosure provides a gate driving circuit and a display panel. The display panel includes a display area and a peripheral area surrounding the display area. At least one gate driving circuit is arranged in the peripheral area. The at least one gate driving circuit includes a plurality of shift register units cascaded in sequence. The plurality of shift register units include first shift register units and second shift register units. The first shift register units and the second shift register units are spaced apart from each other. The number of transistors in the first shift register units is smaller than the number of transistors in the second shift register units.

Abstract: A display device includes a substrate and a first common electrode layer, a pixel electrode layer and a second common electrode layer which are stacked on the substrate in turn; wherein an orthographic projection of the first common electrode layer on the substrate is at least partially overlapped with an orthographic projection of the pixel electrode layer on the substrate, and a first storage capacitor is formed on an overlapping portion of the first common electrode layer and the pixel electrode layer; an orthographic projection of the second common electrode layer on the substrate is at least partially overlapped with the orthographic projection of the pixel electrode layer on the substrate, and a second storage capacitor is formed on an overlapping portion of the second common electrode layer and the pixel electrode layer.

Abstract: An apparatus for virtual avatar generation is provided, including a face encoder, a face fusion engine, a voice encoder, and a voice fusion engine. The face encoder extracts first facial features from the first facial image and then encodes they into M first facial feature vectors and extracts second facial features from the second facial image and then encodes they into M second facial feature vectors. The face fusion engine generates a facial fused feature vector from the facial feature vectors, thereby generating a fused image. The voice encoder extracts first voice features from the first audio clip and then encodes they into N first voice feature vectors and extracts second voice features from the second audio clip and then encodes they into N second voice feature vectors. The voice fusion engine synthesizes a voice fused feature vector from the voice feature vectors, thereby generating a fused voice.

Abstract: A display substrate is provided, including a display substrate that includes a display area and a bezel area; a plurality of scanning signal lines; a gate driver circuit in the bezel area; a plurality of load compensation units in the bezel area, where the load compensation units are between the gate driver circuit and a plurality of pixel units; and a plurality of scanning signal lead wires in the bezel area. At least one load compensation unit includes a compensation capacitor including a first compensation capacitor electrode in a first conductive layer and a second compensation capacitor electrode in a semiconductor layer, and an orthographic projection of the first compensation capacitor electrode on the base substrate at least partially overlaps with an orthographic projection of the second compensation capacitor electrode on the base substrate. The first compensation capacitor electrode is electrically connected to a scanning signal lead wire.

Abstract: A display substrate includes: a first base substrate; scanning lines a side of the first base substrate, extending in a first direction; and arranged in a second direction data lines at the same side of the first base substrate as the scanning lines and in a different layers from the scanning lines, extending in the second direction and arranged in the first direction; a common electrode layer at a side of the scanning lines and the data lines facing away from the first base substrate; and a first light shielding layer in contact with the common electrode layer, and including first light shielding portions extending in the second direction. The first direction intersects with the second direction. The first light shielding portions are in areas between adjacent sub-pixels in the first direction.

Abstract: A biaxially oriented multilayer film having a core layer that includes a polyethylene-based composition. The core layer has: a melt index (I2) that is from 0.2 g/10 min to 5.0 g/10 min; a density that is between 0.930 g/cm3 and 0.956 g/cm3; and an average short chain branch (SCB) level in the portion between log (Mw) of 4.0 to 5.0 (SCBlogMw4-5) that is greater than 3.5 SCB/1000c and less than 10.0 SCB/1000 C. The biaxially oriented multilayer film also includes at least one additional layer that includes a propylene-based composition.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a plurality of pixel regions, and each pixel region corresponds to a pixel. Each pixel region includes sub-regions in at least two rows, the sub-regions in each row include at least two sub-regions, a part of the sub-regions in each pixel region correspond to the sub-pixels of the pixel, and at least one sub-region is an opaque region.

Abstract: A laminate, an article comprising the laminate and a method for preparing the laminate are provided.

Abstract: A display panel relates to the field of display technology, and includes: a first base substrate and a second base substrate arranged oppositely; a liquid crystal layer and a plurality of conductive layers, wherein the liquid crystal layer and the plurality of conductive layers are located between the first base substrate and the second base substrate; and a plurality of heating elements, wherein the plurality of heating elements are distributed in at least one of the conductive layers.

Abstract: Provided are a laminate material, an article comprising the laminate material and a method for preparing the laminate material. The laminate material, comprises a first substrate comprising at least one metalized PE-based film, a second substrate comprising at least one PE-based film, and an adhesive layer adhering the first substrate to the second substrate, wherein the adhesive layer is derived from a two-component solvent-based polyurethane adhesive composition, and wherein the concentration of fatty acids or fatty acid derivatives in the metalized PE-based film is less than 300 ppm, based on the total weight of the metalized PE-based film. The two-component solvent-based polyurethane adhesive composition comprises a polyester polyol component and a polyisocyanate component, wherein the polyol component has 40 wt %-60 wt % of aromatic rings in the backbone, based on the total weight of the polyester polyol and a Mw between 5.000 and 50.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a substrate, the substrate comprising a blind hole area; a buffer layer covering one side of the substrate; an organic film layer provided on the surface of the buffer layer away from the substrate and having a first opening in the blind hole area; a passivation layer provided on the side of the organic film layer away from the substrate and having a second opening in the blind hole area; and a transparent electrode layer covering the passivation layer and the buffer layer in the second opening.

Abstract: Provided is a touch display substrate. The touch display substrate includes a base substrate, including a display region and a non-display region; a plurality of touch electrodes disposed in the display region; and a plurality of signal transmission circuits, a plurality of first control lines, a plurality of second control lines, a target signal line, and a plurality of touch signal lines that are disposed in the non-display region.

Abstract: The present disclosure provides a display substrate and a display apparatus. The display substrate includes a base substrate, including a display region and a frame region located on at least one side of the display region; a transistor, located on the base substrate, wherein the transistor is located in the display region and includes a gate, a first electrode and an active layer; and a protective structure, located on the base substrate, wherein the protective structure is provided in the frame region and close to the display region, and the protective structure is in the same layer as and is made of the same material as at least one of the active layer, the gate or the first electrode.

Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.