Patents by Inventor Jinliang LIU

Jinliang LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11132934
    Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, an output circuit, and a first node control circuit. The input circuit is configured to charge a first node in response to an input signal; the output circuit is configured to output an output signal at an output terminal under control of a level signal of the first node; and the first node control circuit is configured to receive a precharge control signal from a precharge control terminal and charge the first node in response to the precharge control signal before the output terminal outputs the output signal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 28, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yongxian Xie, Jinliang Liu, Hui Wang, Miao Zhang
  • Publication number: 20210209993
    Abstract: The present application provides shift register, gate driver-on-array circuit and driving method thereof, display device. The shift register includes input sub-circuit, output sub-circuit and step-down sub-circuit. The input sub-circuit is configured to, in input stage, charge pull-up node to first voltage level based on signal input from signal input terminal. The output sub-circuit is configured to, in output stage, pull up voltage level at pull-up node to second voltage level. The step-down sub-circuit is configured to, in output stage, pull down voltage level at pull-up node from second voltage level to third voltage level after voltage level at pull-up node is pulled up to second voltage level. The output sub-circuit is further configured to, in output stage, output first clock signal input from first clock signal input terminal through signal output terminal under control of pull-up node.
    Type: Application
    Filed: December 5, 2017
    Publication date: July 8, 2021
    Inventors: Jing SUN, Jinliang LIU, Jian ZHAO, Miao ZHANG
  • Publication number: 20210150969
    Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, an output circuit, and a first node control circuit. The input circuit is configured to charge a first node in response to an input signal; the output circuit is configured to output an output signal at an output terminal under control of a level signal of the first node; and the first node control circuit is configured to receive a precharge control signal from a precharge control terminal and charge the first node in response to the precharge control signal before the output terminal outputs the output signal.
    Type: Application
    Filed: August 16, 2019
    Publication date: May 20, 2021
    Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yongxian Xie, Jinliang Liu, Hui Wang, Miao Zhang
  • Patent number: 10885858
    Abstract: An array substrate, a display panel, a display device and a method for designing the display panel are provided. The array substrate includes a plurality of pixel units, wherein each of the pixel units includes a plurality of sub-pixels, each of the sub-pixels includes a pixel electrode, and the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes arranged in a comb-teeth form, and the sub-pixels of one of the pixel units include at least two sub-pixels. A width of the strip-shaped sub-pixel electrode of any one of the at least two sub-pixels is different from a width of the strip-shaped sub-pixel electrode of any other one of the at least two sub-pixels, and/or an interval between the strip-shaped sub-pixel electrodes of any one of the at least two sub-pixels is different from an interval between the strip-shaped sub-pixel electrodes of any other one of the at least two sub-pixels.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 5, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jilei Gao, Jinliang Liu, Yang Zhang, Xuebing Jiang, Songmei Sun
  • Patent number: 10854130
    Abstract: A gate driving unit includes a first pull-down node control circuit, a second pull-down node control circuit and a pull-up node resetting circuit. The first/second pull-down node control circuit is configured to control a first/second pull-down node to be electrically connected to, or electrically disconnected from, a second/first control voltage end under the control of a potential at a pull-up node. The pull-up node resetting circuit is configured to control the pull-up node to be electrically connected to the second control voltage end under the control of a potential at the first pull-down node, and control the pull-up node to be electrically connected to the first control voltage end under the control of a potential at the second pull-down node.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 1, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng Wang, Jinliang Liu, Songmei Sun
  • Publication number: 20200294441
    Abstract: A gate driving unit includes a first pull-down node control circuit, a second pull-down node control circuit and a pull-up node resetting circuit. The first/second pull-down node control circuit is configured to control a first/second pull-down node to be electrically connected to, or electrically disconnected from, a second/first control voltage end under the control of a potential at a pull-up node. The pull-up node resetting circuit is configured to control the pull-up node to be electrically connected to the second control voltage end under the control of a potential at the first pull-down node, and control the pull-up node to be electrically connected to the first control voltage end under the control of a potential at the second pull-down node.
    Type: Application
    Filed: September 25, 2019
    Publication date: September 17, 2020
    Inventors: Zheng Wang, Jinliang Liu, Songmei Sun
  • Patent number: 10771067
    Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 8, 2020
    Assignee: NEWCOSEMI (BEIJING) TECHNOLOGY CO., LTD
    Inventors: Deyi Pi, Chang Liu, Jinliang Liu
  • Patent number: 10741132
    Abstract: A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 11, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Mo Chen, Jinliang Liu, Wuxia Fu, Huanyu Li, Songmei Sun
  • Publication number: 20200219456
    Abstract: An array substrate, a display panel, a display device and a method for designing the display panel are provided. The array substrate includes a plurality of pixel units, wherein each of the pixel units includes a plurality of sub-pixels, each of the sub-pixels includes a pixel electrode, and the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes arranged in a comb-teeth form, and the sub-pixels of one of the pixel units include at least two sub-pixels. A width of the strip-shaped sub-pixel electrode of any one of the at least two sub-pixels is different from a width of the strip-shaped sub-pixel electrode of any other one of the at least two sub-pixels, and/or an interval between the strip-shaped sub-pixel electrodes of any one of the at least two sub-pixels is different from an interval between the strip-shaped sub-pixel electrodes of any other one of the at least two sub-pixels.
    Type: Application
    Filed: July 13, 2017
    Publication date: July 9, 2020
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jilei GAO, Jinliang LIU, Yang ZHANG, Xuebing JIANG, Songmei SUN
  • Patent number: 10650904
    Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 12, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Xiong Xiong, Rongcheng Liu, Jinliang Liu, Xiaozhe Zhang, Huanyu Li
  • Patent number: 10587274
    Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 10, 2020
    Inventors: Deyi Pi, Chang Liu, Jinliang Liu
  • Publication number: 20200044657
    Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.
    Type: Application
    Filed: November 20, 2017
    Publication date: February 6, 2020
    Inventors: Deyi PI, Chang LIU, Jinliang LIU
  • Patent number: 10541039
    Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 21, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yang Zhang, Jinliang Liu, Mo Chen, Jian Zhao, Jilei Gao, Songmei Sun
  • Publication number: 20190393879
    Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Inventors: Deyi PI, Chang LIU, Jinliang LIU
  • Patent number: 10424249
    Abstract: A pixel driving circuit and a driving method thereof, an array substrate, and a display device. The pixel driving circuit includes a drift suppression unit, a data writing unit, a compensating unit, and a working unit; the drift suppression unit receives a reference control signal and a reference signal; the drift suppression unit is configured to output the reference signal to the compensating unit under control of the reference control signal during a drift suppression period and a resetting period; during the drift suppression period, an electrical potential of the reference signal is smaller than zero.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 24, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Yang Zhang, Jinliang Liu
  • Patent number: 10241145
    Abstract: The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Miao Zhang, Jinliang Liu, Mo Chen, Jing Sun, Songmei Sun
  • Patent number: 10243007
    Abstract: An array substrate, a display panel and display device including the array substrate, and a method of manufacturing the array substrate are provided. The array substrate includes a display area, a plurality of first transistors disposed in the display area, a non-display area disposed at a periphery of the display area and a plurality of second transistors disposed in the non-display area, wherein compared to the plurality of first transistors, an active layer of each second transistor has a smaller thickness.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jilei Gao, Jing Sun, Jinliang Liu, Hongqiang Luo, Zuwen Liu
  • Publication number: 20190080779
    Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 14, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yang ZHANG, Jinliang LIU, Mo CHEN, Jian ZHAO, Jilei GAO, Songmei SUN
  • Publication number: 20190057755
    Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 21, 2019
    Applicants: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Xiong Xiong, Rongcheng Liu, Jinliang Liu, Xiaozhe Zhang, Huanyu Li
  • Patent number: 10192500
    Abstract: Polarity reversion driving method and apparatus of liquid crystal display and a liquid crystal display are provided. In the method, four frames constitute one polarity reversion driving period, in which a first frame and a third frame have a same polarity arrangement with reversed polarities; a second frame and a fourth frame have a same polarity arrangement with reversed polarities; the first frame and the second frame have different polarity arrangements and corresponding pixels in adjacent two frames have complementary charging effects. The apparatus includes a time schedule controller, a logic controller and a source driver. Charging effects of pixels in frames are controlled by setting a polarity arrangement of pixels in each frame so that charging effects of corresponding pixels are complementary in adjacent two frames, thereby relieving the problem of reduced display quality due to inconsistent charging effects of pixels on two sides of data lines.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jinliang Liu, Guangyan Tian