Abstract: An array substrate, a display panel, a display device and a method for designing the display panel are provided. The array substrate includes a plurality of pixel units, wherein each of the pixel units includes a plurality of sub-pixels, each of the sub-pixels includes a pixel electrode, and the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes arranged in a comb-teeth form, and the sub-pixels of one of the pixel units include at least two sub-pixels. A width of the strip-shaped sub-pixel electrode of any one of the at least two sub-pixels is different from a width of the strip-shaped sub-pixel electrode of any other one of the at least two sub-pixels, and/or an interval between the strip-shaped sub-pixel electrodes of any one of the at least two sub-pixels is different from an interval between the strip-shaped sub-pixel electrodes of any other one of the at least two sub-pixels.

Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.

Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.

Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.

Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.

Abstract: A pixel driving circuit and a driving method thereof, an array substrate, and a display device. The pixel driving circuit includes a drift suppression unit, a data writing unit, a compensating unit, and a working unit; the drift suppression unit receives a reference control signal and a reference signal; the drift suppression unit is configured to output the reference signal to the compensating unit under control of the reference control signal during a drift suppression period and a resetting period; during the drift suppression period, an electrical potential of the reference signal is smaller than zero.

Abstract: An array substrate, a display panel and display device including the array substrate, and a method of manufacturing the array substrate are provided. The array substrate includes a display area, a plurality of first transistors disposed in the display area, a non-display area disposed at a periphery of the display area and a plurality of second transistors disposed in the non-display area, wherein compared to the plurality of first transistors, an active layer of each second transistor has a smaller thickness.

Abstract: The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.

Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.

Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

Abstract: Polarity reversion driving method and apparatus of liquid crystal display and a liquid crystal display are provided. In the method, four frames constitute one polarity reversion driving period, in which a first frame and a third frame have a same polarity arrangement with reversed polarities; a second frame and a fourth frame have a same polarity arrangement with reversed polarities; the first frame and the second frame have different polarity arrangements and corresponding pixels in adjacent two frames have complementary charging effects. The apparatus includes a time schedule controller, a logic controller and a source driver. Charging effects of pixels in frames are controlled by setting a polarity arrangement of pixels in each frame so that charging effects of corresponding pixels are complementary in adjacent two frames, thereby relieving the problem of reduced display quality due to inconsistent charging effects of pixels on two sides of data lines.

Abstract: The present disclosure provides an array substrate. The array substrate includes a display region and a plurality of control lines, the display region being divided into a plurality of sub-regions, each sub-region comprising a plurality of pixels, each pixel including a common electrode. Common electrodes in pixels in a sub-region are electrically connected together; common electrodes in two sub-regions are connected by a switching unit; and a control line is connected with the common electrodes in the sub-region to provide a common voltage signal to the common electrodes.

Abstract: A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.

Abstract: This disclosure provides a gate driving unit, comprising an input sub-circuit, a pull-up sub-circuit, a transmission sub-circuit, an output sub-circuit, a reset sub-circuit, a pull-down sub-circuit and a storage sub-circuit, an input signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a fourth clock signal input terminal, a reset signal input terminal, a first level input terminal, a second level input terminal and a gate driving signal output terminal. This disclosure further provides a gate driving circuit and a driving method thereof, as well as a display device.

Abstract: An array substrate, a display panel and display device including the array substrate, and a method of manufacturing the array substrate are provided. The array substrate includes a display area, a plurality of first transistors disposed in the display area, a non-display area disposed at a periphery of the display area and a plurality of second transistors disposed in the non-display area, wherein compared to the plurality of first transistors, an active layer of each second transistor has a smaller thickness.

Abstract: A spacer, a display panel, a method for manufacturing the display panel, and a display device are provided. The spacer includes a plurality of primary spacer portions and a plurality of connection portions. The plurality of primary spacer portions and the plurality of connection portions are arranged on the first substrate, and each connection portion is arranged between the adjacent primary spacer portions, so as to connect the adjacent primary spacer portions.

Abstract: This disclosure provides a gate driving unit, comprising an input sub-circuit, a pull-up sub-circuit, a transmission sub-circuit, an output sub-circuit, a reset sub-circuit, a pull-down sub-circuit and a storage sub-circuit, an input signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a fourth clock signal input terminal, a reset signal input terminal, a first level input terminal, a second level input terminal and a gate driving signal output terminal. This disclosure further provides a gate driving circuit and a driving method thereof, as well as a display device.

Abstract: A pixel driving circuit and a driving method thereof, an array substrate, and a display device. The pixel driving circuit includes a drift suppression unit, a data writing unit, a compensating unit, and a working unit; the drift suppression unit receives a reference control signal and a reference signal; the drift suppression unit is configured to output the reference signal to the compensating unit under control of the reference control signal during a drift suppression period and a resetting period; during the drift suppression period, an electrical potential of the reference signal is smaller than zero.

Abstract: The present application discloses an array substrate including a base substrate, a first signal line layer on the base substrate having a plurality of first signal lines, an insulating layer on a side of the first signal line layer distal to the base substrate, a second signal line layer having a plurality of second signal lines on a side of the insulating layer distal to the first signal line layer; the plurality of second signal lines crossing over the plurality of first signal lines defining a plurality of subpixels, a passivation layer on a side of the second signal line layer distal to the insulating layer, and a test electrode layer having a plurality of test electrodes on a side of the passivation layer distal to the second signal line layer; each of the test electrode electrically connected to one of a first signal line and a second signal line.