Patents by Inventor Jino Chun

Jino Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode
    Patent number: 5001673
    Abstract: A semiconductor dynamic memory device contains circuitry for implementing either page mode or nibble mode access using a selected conductor connection. A clock voltage used in column decoding and outputting is coupled either from the column strobe or the CAS input by a conductor so that the clock voltage is rendered either dependent upon or independent from the cycling of the column strobe.
    Type: Grant
    Filed: August 14, 1989
    Date of Patent: March 19, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Roger D. Norwood, Jino Chun, Pravin P. Patel
  • Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode
    Patent number: 4876671
    Abstract: A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.
    Type: Grant
    Filed: April 6, 1989
    Date of Patent: October 24, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Roger D. Norwood, Jino Chun, Pravin P. Patel
  • Low power clock generator
    Patent number: 4701633
    Abstract: A clock delay circuit of the type used in semiconductor dynamic read/write memory device employs pull-up and pull-down output transistors connected in series between a voltage supply and ground. Excess current in this series path is minimized by a circuit holding the gate of the output pull-up transistor to a low voltage until the gate of the pull-down transistor goes low. Then, the gate of the pull-up transistor is booted above the supply voltage. Also, tendency for the output voltage to rise above ground during the delay period is avoided.
    Type: Grant
    Filed: April 30, 1985
    Date of Patent: October 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Jino Chun