Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode

Abstract

A semiconductor dynamic memory device contains circuitry for implementing either page mode or nibble mode access using a selected conductor connection. A clock voltage used in column decoding and outputting is coupled either from the column strobe or the CAS input by a conductor so that the clock voltage is rendered either dependent upon or independent from the cycling of the column strobe.

Description

BACKGROUND OF THE INVENTION

This invention relates to semiconductor memory devices and more particularly to an improved high-density MOS random access, dynamic read/write memory.

The most widely used semiconductor memory device for computers is the MOS dynamic RAM, such as the 64K-bit device illustrated in U.S. Pat. No. 4,239,993, issued to McAlexander, White and Rao, assigned to Texas Instruments. These devices have traditionally included a "page mode" of operation in which the row address strobe RAS is held low while the column address strobe CAS is toggled, producing faster data output for data located in the same page (same row address but different column address). Now devices are being manufactured having a "nibble mode" of operation in which the RAS and CAS sequence is the same as page mode, but, instead of latching in a new column address each time CAS is toggled, the original column address is used and incremented by 1. Nibble mode is faster, but limited in address range. From a manufacturer's standpoint, production of both page mode and nibble mode devices requires processing two different types of slices, which adds to the cost of both. It is of course preferable to produce a very large quantity of one design, rather than a number of different designs.

Dynamic RAM chips providing either page mode or nibble mode has been described by Shimotovi et al, ISSCC Digest of Technical Papers, p. 228, Feb. 1983, but the selection is made by using different timing inputs, which placed a burden on the system designer.

It is the principal object of this invention to provide improved dynamic random access memory devices, particularly for providing either page mode or nibble mode. Another object is to provide selection between page mode and nibble mode for semiconductor dynamic memory devices which use a low cost manufacturing method, and/or which do not restrict the system designer.

SUMMARY OF THE INVENTION

In accordance with one embodiment of the invention, a semiconductor dynamic memory device uses a metal-level option to give the advantages of high volume and yield in manufacture, as well as insuring equivalent device quality and reliability. Processing of the slices containing the two different parts is identical, except for the different metal-level masks, used in the last steps of the process.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:

FIG. 1 is an electrical schematic diagram in block form of a semiconductor memory device employing features of the invention;

FIGS. 2a-2c are timing diagrams for the device of FIG. 1;

FIG. 3 is a detailed electrical diagram of the nibble/mode/page/mode selector circuitry used in the device of FIG. 1.

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT

With reference to FIG. 1, one example of a semiconductor memory device that employs the selector circuit of the invention is illustrated. This device is formed in a silicon chip 10 containing an array 11 of dynamic one-transistor memory cells. In this embodiment, the array contains "256K" or 262,144 cells, which if not partitioned would be a square array of 512.times.512 cells; the array is broken into eight arrays 11a-11h, however, with each of these containing 256 columns (256 pairs of bit lines) with sixty-four cells per bit line, or 2.times.256.times.64=32,768 cells. A row decoder 12 positioned between the arrays selects 4- of 1024 rows based upon an 8-bit row address received from a set of row address buffers 13 by lines 14. A 4-of-512 column select is performed by a Y decoder 15 which receives a seven bit column address from seven column buffers 16 via lines 17. A set of nine address input terminals 18 is connected to the row and column buffers 13 and 16 by lines 19. The address is multiplexed; the row address is gated into the buffers 13 when a row address strobe signal RAS drops to zero, and the column address is gated into the buffers 16 when a column address strobe signal CAS drops to zero (for a 1-bit read or write). The RAS and CAS signals are applied to the chip by terminals 20 along with a read/write control W, all these signals being connected to a clock generator 21 which produces all of the internal clocks. A supply voltage Vdd, usually +5v, and ground Vss are also applied to the chip 10 by external terminals 20. A single-bit data input terminal 22 and a single-bit data output terminal 23 are connected to an I/O buffer and control circuit 24. A one-of-four column selector 25 connects one of the four sets I/O lines 26 coming from the column decoder to the I/O control 24. This selector 25 receives two column address bits from the buffers 16 by lines 27. The semiconductor chip 10 is mounted in a sixteen-pin package of the standard type.

In FIGS. 2a-2c operations of the memory device are illustrated in a timing diagram. For a single-bit read operation, FIG. 2a, the W signal stays high, the address is valid on terminals 18 during the intervals shown, and data is valid on the output terminal 23 during a period after the RAS and CAS signals drop. At other times, the output circuitry 24 holds the output terminal 23 in a high impedance state. A write operation is signaled by W going low and in this case the data on input terminal 22 must be valid during the period indicated: the data output terminal 23 stays in the high impedance state. The page mode operation of FIG. 2b is defined when RAS stays low and CAS is cycled to gate in a sequence of column addresses. Although shown for read, the page mode operation can be a write instead. The nibble mode, FIG. 2c, is like page mode but the column addresses are "dont's care" after the first column address is latched into the buffers 16. Also, CAS may be toggled faster for nibble mode (compared to page mode) because the 4-bits of data are already in the output circuitry 24 and need not be fetched.

Referring to FIG. 3, a circuit in the column clock generator chain is shown wherein the metal-level selection is used according to the invention. This circuit receives a column clock .phi.C1 which is derived from the CAS signal, and produces an output .phi.C1 which is used in the latches 16, the decoders 15 and 25, and the output circuitry 24 to initiate and propagate latching in the column address, decoding it, and using it to extract the data from the I/O lines from the sense amplifiers and presenting it to the circuitry 24 for output (in a read operation). That is, every time the .phi.C1 clock is cycled, a new column data output (or input) is processed for read (or write); when the .phi.C1 clock stays static, the existing data remains.

The circuit of FIG. 3 uses a push-pull output stage with pull-up transistor 31 and pull-down transistor 32, and an inverter with transistors 33 and 34 for driving the gate of the pull-up. A booting arrangement 35 assures that the gate of the transistor 31 is driven at a high level. An input node 36 is discharged by a RAS-derived clock .phi.R and transistor 37. Then after CAS falls, .phi.C1 goes high enabling transistor 38 and driving node 36 to a high voltage. Every time CAS is toggled, the node 36 is discharged through a transistor 39 which is controlled by CAS through a transistor 40 when a connector 41 is connected to terminal 44. The connector 41 can be built as a metal-level option in the semiconductor chip 10 of FIG. 1. As a selectable metal-level option, the connector 41 can be made to connect the node 43 either to Vdd at terminal 44 or to .phi.C1 feedback at terminal 42. When the connector 41 is in position to connect to the terminal 42, the device is programmed for nibble mode because the voltage .phi.C2 on node 36 is not controlled by CAS after the first access. Thus, the column chain is disabled when in the nibble mode because when .phi.C2 is high, .phi.C1 is low and transistor 40 is held off, decoupling CAS from the transistor 39. For page mode operation the connector 41 is connected to the Vdd terminal 44, which keeps .phi.C2 (and thus output .phi.C1) under CAS control at all times. This connector arrangement allows the rest of the column chain to be activated on each CAS cycle.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications to the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims

1. A semiconductor device comprising:

a memory array having rows and columns of cells for storing data;

column addressing means for selecting a plurality of columns of cells in response to a column address and a column address strobe signal;

data input/output means, coupled to the column addressing means, for inputting data to or outputting data from selected cells among the plurality of columns; and

selector means for selecting either a page mode or a nibble mode of operation, the selector means including clock circuitry for coupling the column address strobe signal to the data input/output means and a connection made during manufacture for rendering a clock produced by the clock circuitry to be either responsive or non-responsive to toggling of the column address strobe signal.

2. A semiconductor device, in accordance with claim 1, wherein the connection includes:

a metal-level connection within the semiconductor device.

3. A semiconductor device, in accordance with claim 1, wherein the connection includes:

a conductor connected between two points on the semiconductor device.

4. A memory circuit comprising:

a memory array including rows and columns of cells for storing data;

column addressing means for selecting a plurality of columns of cells in response to a column address and a column address strobe signal;

data input/output means, coupled to the column addressing means, for writing data to or a reading data from cell selected from the plurality of columns;

selector means for selecting either a page mode or a nibble mode of operation, the selector means including clock circuitry for coupling the column address strobe signal to the data input/output means; and

the selector means rendering a clock produced by the clock circuitry to be either responsive or non-responsive to toggling of the column address strobe signal by a connection placed during manufacture.

5. A memory device, in accordance with claim 4 wherein the connection includes:

a metal-level connection in the device.

6. A memory device, in accordance with claim 4 wherein the connection includes:

a conductor connected between two points on the device.