Abstract: A semiconductor device is disclosed. The semiconductor device has a substrate with a gallium nitride layer (14) disposed over the substrate. A scandium aluminum nitride layer (10) is disposed over the gallium nitride layer. A source (18) is in contact with the gallium nitride layer, and a drain (20) is spaced from the source, wherein the drain is in contact with the gallium nitride layer.

Abstract: A layer of yttrium (Y) and aluminum nitride (AlN) is employed as a back-barrier to improve confinement of electrons within a channel layer of a high electron mobility transistor (HEMT). As HEMT dimensions are reduced and a channel length decreases, current control provided by a gate also decreases, and it becomes more difficult to “pinch-off” current flow through the channel. A back-barrier layer on a back side of the channel layer improves confinement of electrons to improve pinch-off but does not cause a second 2DEG to be formed below the back-barrier layer. The YAlN layer can be lattice-matched to the channel layer to avoid lattice strain, and a thin layer of YAlN provides less thermal resistance than HEMTs made with thicker back-barrier materials. Due to its chemical nature, a YAlN layer can be used as an etch stop layer.

Abstract: Molecular beam epitaxy (MBE) reactor structures for the unit process of n+GaN contact regrowth using ammonia as a nitrogen source are provided. Structures and methods for enhancing evacuation of ammonia in a GaN regrowth process are also provided.

Abstract: A high electron mobility transistor (HEMT) device is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate that includes a buffer layer having a dopant comprising aluminum, wherein the concentration of aluminum within the buffer layer is between 0.5% and 3%. The epitaxial layer further includes a channel layer over the buffer layer and a barrier layer over the channel layer. A gate contact is disposed on a surface of the epitaxial layers. A source contact and a drain contact are also disposed on the surface of the epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.

Abstract: Fabricating high efficiency, high linearity N-polar gallium-nitride (GaN) transistors by selective area regrowth is disclosed. A demand for high efficiency components with highly linear performance characteristics for radio frequency (RF) systems has increased development of GaN transistors and, in particular, aluminum-gallium-nitride (AlGaN)/GaN high electron mobility transistor (HEMT) devices. A method of fabricating a high efficiency, high linearity N-polar HEMT device includes employing a selective area regrowth method for forming a HEMT structure on the Nitrogen-face (N-face) of a GaN buffer, a natural high composition AlGaN/AlN back barrier for carrier confinement, a thick undoped GaN layer on the access areas to eliminate surface dispersion, and a high access area width to channel width ratio for improved linearity. A problem of impurities on the GaN buffer surface prior to regrowth creating a leakage path is avoided by intentional silicon (Si) doping in the HEMT structure.

Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that provide an electron Hall mobility of 1080±5% centimeters squared per volt-second (cm2/V·s) at room temperature for a charge density of 3.18×1013/cm2 and method of making the HEMT device is disclosed. The epitaxial layers include a channel layer made of gallium nitride (GaN), a first spacer layer made of aluminum nitride (AlN) that resides over the channel layer, a first spacer layer made of AlXGa(1-X)N that resides over the first spacer layer, and a first barrier layer made of ScyAlzGa(1-y-z)N that resides over the second spacer layer. In at least one embodiment, a second barrier layer made of AlXGa(1-X)N is disposed over the first barrier layer.

Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer and an aluminum (Al) based layer having an interface with the GaN layer is disclosed. The Al based layer includes Al and an alloying element that is selected from Group IIIB transition metals of the periodic table of elements. The epitaxial layers are disposed over the substrate. A gate contact, a drain contact, and a source contact are disposed on a surface of the epitaxial layers such that the source contact and the drain contact are spaced apart from the gate contact and each other. The alloying element relieves lattice stress between the GaN layer and the Al based layer while maintaining a high sheet charge density within the HEMT device.

Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer and an aluminum (Al) based layer having an interface with the GaN layer is disclosed. The Al based layer includes Al and an alloying element that is selected from Group IIIB transition metals of the periodic table of elements. The epitaxial layers are disposed over the substrate. A gate contact, a drain contact, and a source contact are disposed on a surface of the epitaxial layers such that the source contact and the drain contact are spaced apart from the gate contact and each other. The alloying element relieves lattice stress between the GaN layer and the Al based layer while maintaining a high sheet charge density within the HEMT device.

Abstract: A field-effect transistor having a transconductance (gm) that remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow through the channel layer and an off-state that prevents substantial current flow through the channel layer is disclosed. The field-effect transistor includes a substrate and a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate. The channel layer is disposed over the substrate and comprises a compound semiconductor material that includes at least one element having a concentration that is graded between the proximal boundary and the distal boundary.

Abstract: An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.

Abstract: A field-effect transistor having a transconductance (gm) that remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow through the channel layer and an off-state that prevents substantial current flow through the channel layer is disclosed. The field-effect transistor includes a substrate and a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate. The channel layer is disposed over the substrate and comprises a compound semiconductor material that includes at least one element having a concentration that is graded between the proximal boundary and the distal boundary.

Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that provide an electron Hall mobility of 1080±5% centimeters squared per volt-second (cm2/V·s) at room temperature for a charge density of 3.18×1013/cm2 and method of making the HEMT device is disclosed. The epitaxial layers include a channel layer made of gallium nitride (GaN), a first spacer layer made of aluminum nitride (AlN) that resides over the channel layer, a first spacer layer made of AlXGa(1-X)N that resides over the first spacer layer, and a first barrier layer made of ScyAlzGa(1-y-z)N that resides over the second spacer layer. In at least one embodiment, a second barrier layer made of AlXGa(1-X)N is disposed over the first barrier layer.

Abstract: A field-effect transistor having a transconductance (gm) that remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow through the channel layer and an off-state that prevents substantial current flow through the channel layer is disclosed. The field-effect transistor includes a substrate and a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate. The channel layer is disposed over the substrate and comprises a compound semiconductor material that includes at least one element having a concentration that is graded between the proximal boundary and the distal boundary.

Abstract: A field-effect transistor having a transconductance (gm) that remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow through the channel layer and an off-state that prevents substantial current flow through the channel layer is disclosed. The field-effect transistor includes a substrate and a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate. The channel layer is disposed over the substrate and comprises a compound semiconductor material that includes at least one element having a concentration that is graded between the proximal boundary and the distal boundary.

Abstract: A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

Abstract: An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.

Abstract: The present disclosure relates to a process of forming a semiconductor device with a high thermal conductivity substrate. According to an exemplary process, a semiconductor precursor including a substrate structure, a buffer structure over the substrate structure, and a channel structure over the buffer structure is provided. The channel structure has a first channel surface and a second channel surface, which is opposite the first channel surface, adjacent to the buffer structure, and has a first polarity. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first channel surface. A heat sink carrier is then provided over the high thermal conductivity substrate. Next, the substrate structure and the buffer structure are removed to provide a thermally enhanced semiconductor device with an exposed surface, which has the first polarity.

Abstract: The present disclosure relates to a process of forming a high thermal conductivity substrate for an Aluminum/Gallium/Indium (III)-Nitride semiconductor device. According to an exemplary process, a semiconductor precursor including a substrate structure and a buffer structure is provided. The buffer structure is formed over the substrate structure and has a first buffer surface and a second buffer surface. Herein, the second buffer surface is adjacent to the substrate structure and the first buffer surface is opposite the second buffer surface. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first buffer surface. A heat sink carrier is then provided over the high thermal conductivity substrate. The substrate structure is then substantially removed to provide a thermally enhanced precursor for the III-Nitride semiconductor device.

Abstract: A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

Abstract: A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer is over the substrate and configured to reduce a total strain of the semiconductor device. The channel layer is over the relaxation layer. The polarization compensation layer is between the relaxation layer and the channel layer and configured to reduce a polarization between the relaxation layer and the channel layer. The barrier layer is over the relaxation layer and configured to polarize a junction between the barrier layer and the channel layer to induce a two-dimensional electron gas in the channel layer.