Patents by Inventor Jin Young Lim
Jin Young Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961775Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: November 8, 2022Date of Patent: April 16, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Patent number: 11955471Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.Type: GrantFiled: January 26, 2022Date of Patent: April 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Do, Dal-Hee Lee, Jin-Young Lim, Tae-Joong Song, Jong-Hoon Jung
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Publication number: 20240105108Abstract: A source driver includes a digital-to-analog converter that converts signals corresponding to first and second colors included in digital image data into first and second analog color data voltages, respectively, an output buffer unit including a first output buffer that alternately outputs the first color data voltage and the second color data voltage during one horizontal period, and a controller that controls the digital-to-analog converter and the first output buffer to alternately output the first color data voltage and the second color data voltage corresponding to each horizontal period for each horizontal period. The controller controls the first output buffer such that the second color data voltage is output after the first color data voltage is first output during a first horizontal period, and the first color data voltage is output after the second color data voltage is first output during a subsequent second horizontal period.Type: ApplicationFiled: April 19, 2023Publication date: March 28, 2024Inventors: Hae Kwan SEO, Bon Seog GU, Jin Young ROH, Jae Keun LIM
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Patent number: 11942030Abstract: A source driver includes a digital-to-analog converter that converts signals corresponding to first and second colors included in digital image data into first and second analog color data voltages, respectively, an output buffer unit including a first output buffer that alternately outputs the first color data voltage and the second color data voltage during one horizontal period, and a controller that controls the digital-to-analog converter and the first output buffer to alternately output the first color data voltage and the second color data voltage corresponding to each horizontal period for each horizontal period. The controller controls the first output buffer such that the second color data voltage is output after the first color data voltage is first output during a first horizontal period, and the first color data voltage is output after the second color data voltage is first output during a subsequent second horizontal period.Type: GrantFiled: April 19, 2023Date of Patent: March 26, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hae Kwan Seo, Bon Seog Gu, Jin Young Roh, Jae Keun Lim
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Patent number: 11941637Abstract: Disclosed is a method of processing item sales information by an electronic apparatus including acquiring a purchase request including item information related to an item selected by a user and information related to a payment means, providing a purchase response including approval information corresponding to the purchase request before proceeding with payment through the payment means in response to the purchase request when the information related to the payment means satisfies a first condition, transmitting a release request for the item to a first server; and requesting payment for at least some of an amount corresponding to one or more purchase requests related to the payment means according to an arrival of settlement timing corresponding to the payment means.Type: GrantFiled: March 23, 2021Date of Patent: March 26, 2024Assignee: Coupang Corp.Inventors: Zee Young Min, Ki Hyun Jeong, Il Hyun Seo, Hyun Ju Cho, Jin Hwan Kim, Hyun Yong Jung, Min Yong Yuk, Ho Hyun Lim, Jin Hyuk Kim
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Publication number: 20240080450Abstract: The present invention discloses an image decoding method, the method including generating a candidate list including motion information derived from a spatial neighboring block and a temporal neighboring block adjacent to a current block; deriving motion information of the current block using the candidate list; generating a prediction block of the current block using the derived motion information; and updating the derived motion information in a motion information list, wherein the generating of the candidate list is performed in such a manner as to include at least one information of the motion information included in the updated motion information list in a block decoded before the current block.Type: ApplicationFiled: November 2, 2023Publication date: March 7, 2024Applicants: Electronics and Telecommunications Research Institute, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITYInventors: Jung Won KANG, Ha Hyun LEE, Sung Chang LIM, Jin Ho LEE, Hui Yong KIM, Gwang Hoon PARK, Tae Hyun KIM, Dae Young LEE
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Publication number: 20230343788Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Gi Young Yang, Hyeon Gyu You, Ga Room Kim, Jin Young Lim, In Gyum Kim, Hak Chul Jung
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Patent number: 11735592Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.Type: GrantFiled: September 23, 2020Date of Patent: August 22, 2023Inventors: Gi Young Yang, Hyeon Gyu You, Ga Room Kim, Jin Young Lim, In Gyum Kim, Hak Chul Jung
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Patent number: 11335673Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.Type: GrantFiled: November 15, 2018Date of Patent: May 17, 2022Inventors: Jung-Ho Do, Dal-Hee Lee, Jin-Young Lim, Tae-Joong Song, Jong-Hoon Jung
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Publication number: 20220149032Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Jung-Ho Do, Dal-Hee Lee, Jin-Young Lim, Tae-Joong Song, Jong-Hoon Jung
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Publication number: 20220115406Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: ApplicationFiled: December 24, 2021Publication date: April 14, 2022Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
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Patent number: 11244961Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: GrantFiled: May 30, 2020Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeon Gyu You, In Gyum Kim, Gi Young Yang, Ji Su Yu, Jin Young Lim, Hak Chul Jung
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Patent number: 11239151Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: GrantFiled: May 28, 2020Date of Patent: February 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
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Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit
Patent number: 11101267Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.Type: GrantFiled: June 18, 2019Date of Patent: August 24, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-young Lim, Jae-ho Park, Sang-hoon Baek, Hyeon-gyu You, Dal-hee Lee -
Publication number: 20210193683Abstract: An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.Type: ApplicationFiled: September 23, 2020Publication date: June 24, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Gi Young YANG, Hyeon Gyu YOU, Ga Room KIM, Jin Young LIM, In Gyum KIM, Hak Chul JUNG
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Publication number: 20210134837Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: ApplicationFiled: May 30, 2020Publication date: May 6, 2021Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
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Patent number: 10990740Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.Type: GrantFiled: April 9, 2019Date of Patent: April 27, 2021Inventors: Jin-Tae Kim, Sung-We Cho, Tae-Joong Song, Seung-Young Lee, Jin-Young Lim
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Publication number: 20200294905Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
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Patent number: 10672702Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: GrantFiled: June 6, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
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Publication number: 20200050728Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.Type: ApplicationFiled: April 9, 2019Publication date: February 13, 2020Inventors: JIN-TAE KIM, Sung-We Cho, Tae-Joong Song, Seung-Young Lee, Jin-Young Lim