Abstract: An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper interconnects 90.

Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.

Abstract: An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer (116). The surface of the first portion of the copper film (118) is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film (118) is electrochemically deposited.

Abstract: The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of copper oxide (105) over the deposited copper seed layer (110) by exposure to a substantially copper-free reducing agent solution (120), such that the copper oxide (105) is substantially converted to elemental copper, followed by electrochemical deposition of a second copper layer (125) over the copper seed layer (110). Such methods and resulting conductive structures thereof may be advantageously used in methods to make integrated circuits comprising interconnection metal lines.

Abstract: The present invention provides, in one embodiment, a method of making thin uniform ternary diffusion barrier layers 150. The method includes introducing first 105, second 135, and third 145 deposition gases one at a time into a chamber 110 to form a conformal ternary layer 150 within an opening 120 located in a dielectric layer 130. Such ternary diffusion barrier layers 150 may be advantageously used in integrated circuit fabrication.

Abstract: The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer (114) on top of a native oxide layer above a silicide layer (110) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer (110) and reduce excess silicon consumption. The temperature range can be greater than 350° C. and less than 615° C., but is optimal between 485° C. to 550° C.

Abstract: A pre-ECD wet surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with a water-based solution to remove surface contamination (122) and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).

Abstract: A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel suicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: A novel nickel self-aligned silicide (SALICIDE) process technology (80) adapted for CMOS devices (54) with physical gate lengths of sub-40 nm. The excess silicidation problem (52) due to edge effect is effectively solved by using a low-temperature, in-situ formed Ni-rich silicide, preferably formed in a temperature range of 260-310° C. With this new process, excess poly gate silicidation is prevented. Island diode leakage current and breakdown voltage are also improved.

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract: In situ nitridation of a thin layer of either silicon or tungsten provides an adhesive layer for bulk deposition of tungsten. Alternatively, a thin layer of silicon can be deposited directly on a dielectric, then reacted with WF6 to replace the silicon with tungsten, which provides a nucleation layer for bulk tungsten deposition.

Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). A layer of cobalt (32) is deposited onto a silicon region (104, 106, 108) and annealed to form a cobalt silicide layer (118, 120, 122). Silicon layers (124, 126, 128) are selectively deposited onto the cobalt silicide layers (118, 120, 122). The semiconductor device (100) is annealed to form disilicide layers (130, 132, 134) from the cobalt silicide layers (118, 120, 122) and the silicon contained in silicon regions (104, 106, 108) and silicon layers (124, 126, 128).

Abstract: Two barrier layers are used for a via or contact. A thin CVD barrier (124) (e.g., SiN, TiSiN, TaSiN, etc.) is deposited over a structure including within a via or contact hole (106). A sputter etch is then performed to remove the CVD barrier (124) at the bottom of the via/contact. A second barrier (126) is deposited after the sputter etch. The second barrier (126) comprises a lower resistivity barrier such as Ta, Ti, Mo, W, TaN, WN, MoN or TiN since the second barrier remains at the bottom of the via or contact. A metal fill process can then be performed.

Abstract: A pre-ECD wet surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with a water-based solution to remove surface contamination (122) and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (102), forming a dielectric layer (104) over the semiconductor substrate (102), and etching a trench structure (106) or a via structure (106) in the dielectric layer (104) to expose a portion of a surface of the semiconductor substrate (102). The method also includes the steps of treating a surface (104a) of the dielectric layer (104) with an adhesion solution, such as a reactive plasma including hydrogen, and forming a diffusion barrier layer (110) over the dielectric layer (104). Moreover, the adhesion solution chemically interacts with the surface (104a) of the dielectric layer (104) and enhances or increases adhesion between dielectric layer (104) and diffusion barrier layer (110).

Abstract: The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer (114) on top of a native oxide layer above a silicide layer (110) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer (110) and reduce excess silicon consumption. The temperature range can be greater than 350° C. and less than 615° C., but is optimal between 485° C. to 550° C.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). A layer of cobalt (32) is deposited onto a silicon region (104, 106, 108) and annealed to form a cobalt silicide layer (118, 120, 122). Silicon layers (124, 126, 128) are selectively deposited onto the cobalt silicide layers (118, 120, 122). The semiconductor device (100) is annealed to form disilicide layers (130, 132, 134) from the cobalt silicide layers (118, 120, 122) and the silicon contained in silicon regions (104, 106, 108) and silicon layers (124, 126, 128).