Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal.

Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: A high pass filter circuit having a signal input terminal and a signal output terminal. The high pass filter circuit is provided with a voltage source, first and second inverters, and a capacitor. The voltage source provides a DC bias voltage. The first inverter couples to the voltage source to invert the DC bias voltage. The second inverter couples to the first inverter and a signal output terminal respectively. The second inverter inverts the DC bias voltage inverted by the first inverter to provide the DC bias voltage to the signal output terminal. The second inverter also provides large impedance at the signal output terminal. The capacitor is coupled between the signal input terminal and the signal output terminal to provide a low corner frequency in cooperation with the second inverter. The circuit further comprises an operational amplifier.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.